A1B 260 03 Search Results

Contextual Info: "HYUNDAI HY67V18110/111 64K X 18 Bit SYNCHRONOUS CMOS SRAM PRELIMINARY DESCRIPTION This device integrates high-speed 64K x18 SRAM core, address registers, data input registers, a 2-bit burst ad­ dress counter and Non-pipelined output. All synchronous inputs pass through registers controlled by a posrtiveedge triggered clock K .

81C61

Contextual Info: 1 111111111111111 11111 1 111111111111111 1 111111111111111 1 111111111111111 1 1 1234536787119ABACDEFA1D91111111 1 11111111 1 11111111 1 11 A1C 123314567891A758BCD814E1F3D167D1F1C5A36 AB1DA167 4DE !"#$%168812&' 1291CC1!"#1AABA9

74HCT139

Contextual Info: TECHNICAL DATA IN74LV139 Dual 2-to-4 line decoder/demultiplexer; inverting N SUFFIX PLASTIC The IN74LV139 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HCT139. The74LV139 is dual 2-to-4 line decoder/demultiplexer . This device has two independent decoders, each accepting two binary

74HC139a

Abstract: DL129 LS139 MC54HCXXXAJ MC74HCXXXAD MC74HCXXXAN 74HC139AD
Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA MC54/74HC139A Dual 1-of-4 Decoder/ Demultiplexer High–Performance Silicon–Gate CMOS The MC54/74HC139A is identical in pinout to the LS139. The device inputs are compatible with standard CMOS outputs; with pullup resistors,

MIL-S-3950

Abstract: 2TL1-12
Contextual Info: if LjJ g: MICRO SWITCH FREEPORT. IL L IN O IS . A OF D IV IS IO N fed . uj LO CNJ C A TA LO G L IS TIN G 2 T L 1 -1 2 SWITCH-T0GGLE U S A HONEYW ELL S E R IE S CHART 1 MFC. CODE »182» T H IS D R A W I N G C O V E R S A P R O P R I E T A R Y I T E M A N D IS T H E P R O P E R T Y O F M IC R O SWI TC H. A D I V I S I O N O F

TC538000F

Contextual Info: s s S b P & & *& *& & & V~'+fr* " * ' w •vi TOS H IB A LfrGIC/NEIIORY* “ trEET r ^0^7240 G 0 2 1 elQ4 1 • T0S2 8M BIT (1 M W O R D X 8 BIT) CM O S M A SK RO M DESCRIPTION The TC538000P/F is a 8,388,608 bits read only memory organized as 1,048,576 words by 8blts.

AC139

Abstract: C139 IN74AC139N 0835 CMOS SWITCHING
Contextual Info: TECHNICAL DATA IN74AC139 Dual 1-of-4 Decoder/Demultiplexer The IN74AC139 is identical in pinout to the LS/ALS139, HC/HCT139. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALS outputs. This device consists of two independent 1-of-4 decoders, each of

74hc139a

Contextual Info: MOTOROLA SC 11E 0 § LOGIC OGflCHE*! T | Order this data sheet by MC54HC139A/D MOTOROLA SEM ICONDUCTOR TECHNICAL DATA T - 6 7 - 2 I - 5 Í ' M C54/74HC139A Advanced Information J SU FFIX CERAMIC CA SE 620-09 Dual 1-of-4 Decoder/ Demultiplexer High-Perform ance Silicon-G ate CM OS

Contextual Info: CMOS SRAM KM6164000B Family Document Title 256Kx16 bit Low Power CMOS Static RAM Revision No. History Draft Data Remark 0.0 Initial d ra ft June 28, 1996 Advance 0.1 Revise - Die name change ; A to B September 19, 1996 Preliminary 1.0 Finalize December 17, 1996

Contextual Info: Preliminary KM68V4000B, KM68U4000B Family CMOS SRAM 512Kx8 bit Low Pow er & Low Vcc CMOS Static RAM FEATURE SUMMARY GENERAL DESCRIPTION • Process Technology : 0.4pm CMOS T he K M 68V 4000B and K M 68U 4000B fam ily are • Organization : 512K x 8 fabricated by SAMSUNG’S advanced CM O S process

cs 308

Abstract: KM68U4000A
Contextual Info: KM68U4000A CMOS SRAM ELECTRONICS 512Kx8 bit Low Power & Low Vcc CMOS Static RAM FEATURE SUMMARY GENERAL DESCRIPTION • Process Technology : 0.4 um CMOS • Organization : 512Kx 8 • Power Supply Voltage KM68V4000A Family : 3.3 +/- 0.3V KM68U4000A Family : 3.0 +/- 0.3V

9114 static ram

Abstract: dallas ds1280 a17b 68-PIN DS1280 DS1280Q-68 TD1220
Contextual Info: » A L L A S SEMICONDUCTOR CORP 31E D B HblMlBO 0003*133 0 ES DAL O S 1280 • W toàia^ M M éa^ M ni iii ii ì r -iiiJL.V^-r ¿ « .,- Mt. -«h. . '.riti , , tM . \* ^ * 5 0~7 E i£ a « a 081280 DALLAS 3-Wire to Bytewide Converter Chip semiconductor

LM 3919

Contextual Info: LED HIGH POWER CoB Product Series LED HIGH POWER CoB Product Series Data Sheet Created Date: 02 / 06 / 2013 Revision: 2.0, 05 / 21/ 2013 1 BNC-OD-C131/A4 Created Date : 05/26/2007 Revison : 1.01, 05/26/2008 LED HIGH POWER CoB Product Series 1. Description

IC 4012

Abstract: 4012 IC ci 4012 ALVCH16260 IDT74ALVCH16260 SO56-2 TH4012
Contextual Info: 3.3V CMOS 12-BIT TRI-PORT BUS EXCHANGER IDT74ALVCH16260 ADVANCE INFORMATION Integrated Device Technology, Inc. 12-bit latched bus multiplexers/transceivers for use in highspeed microprocessor application. These Bus Exchangers support memory interleaving with latched outputs on the B

55AX1000

Abstract: FP-1-35-G-10 FP-1-27-G-10 10A3500 10A35 A3600 1-GUSVT-610 A1B ABB 2-GSVT-48-A 2-GUSVT-410
Contextual Info: Variable Area Flowmeter, Glass Tube Models A3500 & A3600 Specification DataFile •■ Removable metering tube – for range changing or cleaning without removing meter from line ■■ External retaining spring and equal area ends on tube – prevents the tube moving under pressure,

Contextual Info: D S 1647/D S 1S 47P PHELlMiNARY f iA I • A C - Nonvolatile Timekeeping RAM FEATURES PIN ASSIGNMENT DS1647/DS1647P A I6 B 2 A14 §3 A l2 • Clock registers are accessed identical to the static RAM. These registers are resident In the eight top RAM locations.

Contextual Info: CMOS SRAM KM68V1000B, KM68U1000B Family 128Kx8 bit Low Power & Low Vcc CMOS Static RAM FEATURE SUMMARY GENERAL DESCRIPTION • Process T ec h n o lo g y : 0.6 um C M O S T h e K M 6 8 V 1 0 0 0 B and K M 6 8 U 1 0 0 0 B fam ily are fabricated • O rg a n iz a tio n : 1 2 8 K x 8

HY5117400

Abstract: WD41 HY5117400JC cs40
Contextual Info: HY5117400 Series «H YUND AI 4M x 4-bit CMOS DRAM DESCRIPTION The HY5117400 is the new generation and fast dynamic RAM organized 4,194,304 x 4-bit. The HY5117400 utilizes Hyundai’s CMOS silicon gate process technology as well as advanced circuit techniques to provide wide operating

Contextual Info: ><M y i l u n fi i H Y 5 1 V 4 4 1 O B S e r ie s 1M x 4-bit CMOS DRAM with Write-Per-Bit PREUMINARY DESCRIPTION The HY51V4410B is the new generation and fast dynamic RAM organized 1,048,576 x 4-bit with function of Write-Per-Bit. The HY51V4410B utilizes Hyundai's CMOS silicon gate process technology as well as advanced

pin diagram of ic 6260

Contextual Info: FAST CMOS 12- BI T TRI - PORT BUS E X C H A N G E R IDT54/74FCT16260AT/CT/ET IDT54/74FCT162260AT/CT/ET FEATURES: DESCRIPTION: • C o m m o n f e a t ur e s : The F C T 16260A T/C T/E T and the F C T 162260AT/C T/ET Tri-Port Bus Exchangers are high-speed 12-bit latched bus

420 Diode 2ba

Abstract: land pattern for tvSOP
Contextual Info: 3.3V CMOS 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH WITH 3-STATE OUTPUTS FEATURES: - 0.5 MICRON CMOS Technology - Typical tsK o (Output Skew) < 250ps - IDT74AL VC16260 D E S C R IP T IO N : This 12-bit to 24-bit multiplexed D-type latch is built using advanced

sel 4039

Contextual Info: 3.3V CMOS 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH WITH 3-STATE OUTPUTS AND BUS-HOLD FE A T U R E S : - 0.5 MICRON CMOS Technology - Typical - ESD > 2000V per MIL-STD-883, Method 3015; tsK o (Output Skew) < 250ps > 200V using machine model (C = 200pF, R = 0)

Contextual Info: 3.3V CMOS 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH WITH 3-STATE OUTPUTS AND BUS-HOLD FEATURES: - 0.5 MICRON CMOS Technology - Typical tsK o (Output Skew) < 250ps - ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) -

Contextual Info: SN65LVDS386/388A/390, SN65LVDT386/388A/390 SN75LVDS386/388A/390, SN75LVDT386/388A/390 HIGH-SPEED DIFFERENTIAL LINE RECEIVERS SLLS394D – SEPTEMBER 1999 – REVISED MAY 2001 D D D D D D D D D D D Four ’390 , Eight (‘388A), or Sixteen (‘386) Line Receivers Meet or Exceed the