A8 JH Search Results

0C314

Abstract: H7 RF IC-311 SP 6554 A adcb 27 TI BB cross MC68HC11D3 MC68HC711D3 S002D OC310
Contextual Info: MC68HC11D3RG/AD MC68HC11D3 MC68HC711D3 PROGRAMMING REFERENCE GUIDE M MOTOROLA 192 BYTES STATIC RAM MULTIPLEXED ADDRESS/DATA BUS • A8 A15À A D 7 - -ADO À y y y DATA DIRECTION REGISTER C DATA DIRECTION REGISTER B PO RTC PO RTB A A

0C314

Abstract: OC310 TSX 07 2B 1628
Contextual Info: MC68HC11D3RG/AD MC68HC11D3 MC68HC711D3 PROGRAMMING REFERENCE GUIDE M MOTOROLA 192 BYTES STATIC RAM MULTIPLEXED ADDRESS/DATA BUS • A8 A15À A D 7 - -ADO À y y y DATA DIRECTION REGISTER C DATA DIRECTION REGISTER B PO RTC PO RTB A A

arbitration scheme

Contextual Info: AIC-301 adaptec, inc. Dual-Port Buffer Controller PRELIMINARY Direct 16-Bit Buffer Addressing n Fully Downward Compatible With The AIC-300F <<<<u : o « ' î n w r- srco o jf— o ^ •>» 'T ^ / A4 A5 A6 A7 SHPOR-A8 SDP OR -A9 ALE -RST PORT A REQ -CLK AIO

Contextual Info: TM4256EC4, TM4257EC4 262.144 BY 4-BIT DYNAMIC RAM MODULES SEPTEMBER 9 185 - REVISED NOVEMBER 198E C S IN G LE -IN LINE P AC K A G E 2 6 2 ,1 4 4 X 4 Organization TO P V IE W Single 5-V Supply <10% Tolerance) A8 22-Pin Single-in-Line Package (SIP) VDD D1

256k 30-pin SIMM

Abstract: 30-pin simm memory MT8259 30-pin SIMM
Contextual Info: |U|IC=RON MT8259 256K X 8 DRAM DRAM MODULE PIN ASSIGNMENT Top View OPTIONS Vcc CÄ5 DQ1 AO A1 DQ2 A2 A3 Vss DQ3 A4 A5 DQ4 A6 A7 DQ5 A8 NC NC DQ6 MARKING • Timing 80ns access 100ns access 120ns access 150ns access • Packages: Leadless 30-pin SIMM Leaded 30-pin SIP

AC82PM45

Abstract: AC82GM45 KB926 AF82801IBM SLB8Q N10M-GE1-S G545A1 NV10M-GS tps51620 LA-5081P KIWA7
Contextual Info: A B C D E 1 1 KIWA7/A8 2 2 Schematics Document Mobile Penryn uFCPGA with Intel Cantiga_GM/PM+ICH9-M core logic 3 3 REV:0.4 4 4 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2008/03/25 Deciphered Date 2008/04/ Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

1221H

Abstract: A12C White Microelectronics 14 PIN DIP WS128K8-XCX
Contextual Info: WHITE /MICROELECTRONICS WS128K8-XCX 128Kx8 SRAM MODULE FEATURES FIG. 1 PIN CONFIGURATION TOP VIEW n c E 1 W 32 13 Vcc A16C 2 31 H A15 A 14C 3 30 □ nc A 1 2 |I 4 29 U we A7 C 5 27 □ A8 A5Ü 7 26 □ A9 A4 C 8 25 □ A11 C9 24 □ ÖE A 2 C 10 23 □ A10

Contextual Info: DALLAS SEMICONDUCTOR DS2064 8K x 8 3V Operation Static RAM PIN ASSIGNMENT FEATURES • Low power CMOS design • Standby current NC C 1 28 3 Vcc A12 C 2 27 3 WË A7 C 3 26 3 CE2 A6 C 4 25 D A8 3 3 3 3 3 3 3 3 3 3 50 nA max at tA = 25°C Vcc = 3.0V 100 nA max at tA = 25°C Vcc = 5.5V

S2L00

Contextual Info: 256K x 4 molale V id e o R A M M V M 4 2 5 9 -1 0 /1 2 Issue 2.0 : February 1992 P R E L IM IN A R Y S e m ic o n d u c to r Inc. Pin Definition 262,144 X 4 CMOS Fully Featured Video RAM SC SI01 SI02 DT/OE W1/I01 W 2/I02 WB/WE NC RAS A8 A6 A5 A4 Vcc Features

Static ram 2149

Abstract: 2149 STATIC RAM
Contextual Info: MOS LSI TMS 2149 JL, NL, FPL FAST 1024-W0RD BY 4-BIT STATIC RAM J A N U A R Y 1982 - R E V IS E D M A Y 1 98 2 TM S 2149 18-PIN PLASTIC A N D C E RA M IC D U A L -IN -L IN E PACKAGES 1024 X 4 Organization TOP VIEW Q U l8 3 V CC A2 Q 2 17 A8 16 A4 AlC 3

rpack 10k

Abstract: t1 BC547 icsp1 rpack 10k x9 CD 7805 icsp pic zif CD4015 ZIF-32 74HC04 93C468
Contextual Info: 1 D 2 3 4 D STB INIT BUSY ACK BUSY PRINTER 1 15 DB25 D4 D5 D6 D7 S4 2 9 10 D Vcc1 2 12 3 Q6 Q7 Q8 P/S CLK R2 10k CLK R Q0 Q1 Q2 Q3 5 4 3 10 A4 A5 A6 A7 CD 4015 U5A 15 CLK D 1 14 CLK RST Q0 Q1 Q2 Q3 13 12 11 2 A8 A9 A10 A11 5 4 3 10 A12 A13 A14 A15 13 12 11

Contextual Info: JHPD23C8000 8,388,608-Bit Mask-Programmable CMOS ROM NEC NEC Electronics Inc. Description Pin Configuration T h e /JP D 23 C 8 000 is a 8 ,3 8 8 ,6 0 8 -b it R O M fa b ric a te d w ith C M O S s ilic o n -g a te techn olo gy. It is s ta tic in o p e ra tio n

Contextual Info: 1# •I SURFACE MOUNT QUADRATURE HYBRID 8 0 -1 6 0 MHz MODEL JHS-119 Fully Hermetic Package Octave Bandwidth Low VSWR — 1.3:1 Guaranteed Specifications* From - 5 5 °C to + 8 5 ° C Frequency Range Insertion Loss (Less coupling) 80-160 MHz 0.75 dB Max*

W6 Diode

Contextual Info: SKN 2F50 THYRISTOR BRIDGE,SCR,BRIDGE Stud Diode Fast Recovery Rectifier Diode SKN 2F50 Features # $%&'' *+,)()- *.&(/) # $+01 ()*+,)(2 # 34 1+ 5666 7 (),)(8) ,+'1&/) # 9)(%)1:* %)1&' *&8) ;:1. /'&88 # :<8='&1+( >.()&-)- 81=- ?$@ AB +( 5CDEFG 3HI $JHK &<+-) 1+ 81=-

NEC marking code A4X

Abstract: 2XD marking
Contextual Info: DATA SHEET NEC MOS INTEGRATED CIRCUIT 8M-bit Synchronous GRAM Description The //PD481850 is a synchronous graphics memory SGRAM organized as 131,072 words x 32 bits x 2 banks random access port. This device can operate up to 100 MHz by using synchronous interface. Also, it has 8-column Block Write function

MSM54V25632A

Abstract: MSM54V25632A-10 MSM54V25632A-12 QFP100-P-1420-0
Contextual Info: E2L0051-27-Z4 O K I Semiconductor MSM54V25632A Previous version: May. 1997 ~ 131,072-Word x 32-Bit x 2-Bank Synchronous Graphics RAM DESCRIPTION The MSM54V25632A is a synchronous graphics random access memory organized as 128 K words x 32 bits x 2 banks. This device can operate up to 100 MHz by using synchronous interface. In addition, it has 8-column

54V25632A

Contextual Info: E2L0051-27-Z4 O K I Semiconductor Previous version: May. 1997 M SM 54V25632A 131,072-Word x 32-Bit x 2-Bank Synchronous Graphics RAM DESCRIPTION The MSM54V25632A is a synchronous graphics random access memory organized as 128 K words x 32 bits x 2 banks. This device can operate up to 100 MHz by using synchronous interface. In addition, it has 8-column

Contextual Info: M t n t» DENSE-PAC MICROSYSTEMS "7\ /H-Dênsus a ^ 128 Aa dpdd32mx4riay5 Megabit CM OS DDR SDRAM High Density Memory Device d pd d 32 m X 4 R S A Y 5 ADVANCED INFORMATION DESCRIPTION: Jhe/k-'D eH JH j series is a family of interchangeable memory devices.

LH3330

Contextual Info: LIGITEK ELECTRONICS CO.,LTD. Property of Ligitek Only OFFICE:7F.,NO.208,SEC.3,JHONGYANG Rd.,Tucheng City Taipei Hsien,Taiwan R.O.C TEL: 02 22677686(REP) FAX:(02)22675286,(02)22695616 建興 LED ARRAY LA213W/H DATA SHEET DOC. NO : QW0905- LA213W/H REV. : B

aab3n

Contextual Info: HM5283206 Series 131,072-word x 32-bit x 2-bank Synchronous Graphic RAM HITACHI ADE-203-223A Z Rev. 1.0 May. 30, 1996 Description AH inputs and outputs signals refers to the rising edge of the clock input. The HM5283206 provides 2 banks to realize better perform ance. 8 column block write function and write per bit function are

Contextual Info: ADE-203-223 A (Z) * HM5283206 Series 131,072-word x 32-bit x 2-bank Synchronous Graphic RAM Preliminary HITACHI — Self refresh (1024 refresh cycles: 16 ms) All inputs and outputs signals refers to the rising edge of the clock input. The HM5283206 provides

UPD424280

Contextual Info: DATA SHEET ¿ ^ £ £ £ J D 4 5 0 7 4 r 7S4 inece MOS INTEGRATED CIRCUIT ¿¿PD42S4280, 424280 4 M BIT DYNAMIC RAM 256 K-WORD BY 18-BIT, FAST PAGE MODE, BYTE READ/WRITE MODE DESCRIPTION The ¿¿PD42S4280, 424280 are 262 144 words by 18 bits dynamic CMOS RAMs. The fast page mode and byte

texas F245

Contextual Info: SN54F245, SN74F245 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SDFS010A- MARCH 1987 - REVISED OCTOBER 1993 SN54F245 . . . J PACKAGE SN74F245 . . . DB, DW, OR N PACKAGE TOP VIEW 3-State Outputs Drive Bus Lines Directly Package Options Include Plastic Small-Outline (SOIC) and Shrink

nec eric-2

Abstract: UPD481
Contextual Info: PRELIMINARY DATA SHEET NEC / MOS INTEGRATED CIRCUIT ¿¿PD4 8 1 8 5 0 8 M-bit Synchronous GRAM for Rev.L Description The /jPD 481 850 is a synchrono us graphics m em o ry SG R AM organized as 131,072 w ords x 32 b its x 2 banks random access port. T his device can ope rate up to 100 M Hz b y using synchronous interface.