ACCUNET Search Results

MT8952

Abstract: MT8976 MT8977 MT8977AC MT8977AE MT8977AP MT8979 MT8980 SLC96
Contextual Info:  ISO-CMOS ST-BUS FAMILY MT8977  T1/ESF Framer Circuit ACCUNET T1.5 Preliminary Information Features • • • • • • • • • • • • • • ISSUE 2 D3/D4 or ESF framing and SLC-96 compatible Two frame elastic buffer with jitter tolerance

MT8952

Abstract: MT8976 MT8977 MT8977AE MT8977AP MT8979 MT8980 SLC96 Alternate Mark Inversion
Contextual Info: ISO-CMOS ST-BUS FAMILY MT8977  T1/ESF Framer Circuit ACCUNET T1.5 Preliminary Information Features • • • • • • • • • • • • • • ISSUE 4 D3/D4 or ESF framing and SLC-96 compatible Two frame elastic buffer with jitter tolerance

Contextual Info: ISO-CMOS ST-BUS FAMILY MT8977  T1/ESF Framer Circuit ACCUNET T1.5 Preliminary Information Features • • • • • • • • • • • • • • ISSUE 4 D3/D4 or ESF framing and SLC-96 compatible Two frame elastic buffer with jitter tolerance

MT8952

Abstract: MT8976 MT8977 MT8977AC MT8977AE MT8977AP MT8979 MT8980 SLC96
Contextual Info:  ISO-CMOS ST-BUS FAMILY MT8977  T1/ESF Framer Circuit ACCUNET T1.5 Preliminary Information Features • • • • • • • • • • • • • • ISSUE 2 D3/D4 or ESF framing and SLC-96 compatible Two frame elastic buffer with jitter tolerance

Contextual Info: ISO-CMOS ST-BUS FAMILY M ITEL MT8977 T1/ESF Framer Circuit ACCUNET T1.5 Preliminary Information Features • • ISSUE 2 D3/D4 or ESF framing and SLC-96 compatible Two frame elastic buffer with jitter tolerance improved to 156 III Insertion and detection of A, B, C, D bits,

Contextual Info: • MITEL b 5 4 c1 3 7 D 0 0 0 7 ^ 0 M TT ■ M IT C MT3977 T1 /ESF Framer Circuit ACCUNET T1.5 ISO-CMOS ST-BUS” FAM ILY Preliminary Information ^4C4Aä«i!tW44W:i>'>vW Features Pin Connections • D3/D4 or ESF framing and SLC-96 compatible. • Two frame elastic buffer with jitter tolerance

MT8940

Abstract: MT8952 MT8976 MT8977 MT8977AE MT8977AP MT8979 MT8980
Contextual Info: ISO-CMOS ST-BUS FAMILY MT8977  T1/ESF Framer Circuit ACCUNET T1.5 Preliminary Information Features • • • • • • • • • • • • • • ISSUE 4 D3/D4 or ESF framing and SLC-96 compatible Two frame elastic buffer with jitter tolerance

MT8940

Abstract: MT8952 MT8976 MT8977 MT8977AE MT8977AP MT8979 MT8980
Contextual Info: ISO-CMOS ST-BUS FAMILY MT8977  T1/ESF Framer Circuit ACCUNET T1.5 Preliminary Information Features • • • • • • • • • • • • • • ISSUE 4 D3/D4 or ESF framing and SLC-96 compatible Two frame elastic buffer with jitter tolerance

Contextual Info: ISO -C M O S ST-BUS FAMILY • V IIT E L MT8977 T1/ESF Framer Circuit ACCUNET® T1.5 Prelim inary Inform ation s e m ic o n d u c t o r Features ISSUE 4 D3/D4 or ESF fram ing and S LC -96 com patible Two fram e elastic buffer w ith jitte r tolerance

MT8977

Abstract: slc 500 circuit diagram MT8952 MT8976 MT8977AE MT8977AP MT8979 MT8980
Contextual Info: ISO -C M O S ST-BUS FAMILY • V IIT E L T1/ESF Framer Circuit ACCUNET® T1.5 Prelim inary Inform ation s e m ic o n d u c t o r Features • • • • • • • • • • • • MT8977 ISSUE 4 D3/D4 or ESF framing and SLC-96 compatible Two frame elastic buffer with jitte r tolerance

60-ST

Abstract: MT8940 MT8952 MT8976 MT8977 MT8977AE MT8977AP MT8979 MT8980 phase status word
Contextual Info: ISO-CMOS ST-BUS FAMILY MT8977  T1/ESF Framer Circuit ACCUNET T1.5 Preliminary Information Features • • • • • • • • • • • • • • ISSUE 4 D3/D4 or ESF framing and SLC-96 compatible Two frame elastic buffer with jitter tolerance

Contextual Info: ISO CMOS ST-BUSTM Family MT8977  T1/ESF Framer Circuit ACCUNET T1.5 Data Sheet Features September 2005 • D3/D4 or ESF framing and SLC-96 compatible • Two frame elastic buffer with jitter tolerance improved to 156 UI • Insertion and detection of A, B, C, D bits,

Contextual Info: ISO CMOS ST-BUSTM Family MT8977  T1/ESF Framer Circuit ACCUNET T1.5 Data Sheet Features September 2005 • D3/D4 or ESF framing and SLC-96 compatible • Two frame elastic buffer with jitter tolerance improved to 156 UI • Insertion and detection of A, B, C, D bits,

Contextual Info: ISO-CMOS ST-BUS FAMILY MT8977  T1/ESF Framer Circuit ACCUNET T1.5 Preliminary Information Features • • • • • • • • • • • • • • ISSUE 4 D3/D4 or ESF framing and SLC-96 compatible Two frame elastic buffer with jitter tolerance

transistor cms 6BW

Abstract: g2v2 relay 4 digit 7 segment calculator lcd display pin BIT 31936 g2v2 transistor 5bw A7102A 6BW 87 automatic dialer sd 7402
Contextual Info: DEFINITY Enterprise Communications Server and System 75 and System 85 Terminals and Adjuncts Reference 555-015-201 Comcode 108603994 Issue 11 December 1999 Copyright  1999, Lucent Technologies All Rights Reserved Printed in USA Notice Every effort was made to ensure that the information in this book was

A23 1101 01A

Abstract: E1-PCM-30 Bt8370KPF RJ48C EE - 19c TRANSFORMER E1-PCM-30 ch chips 65554 RDL2 MC68302 TR-303
Contextual Info: Bt8370/75/76 Fully Integrated T1/E1 Framer and Line Interface The Bt8370/75/76 is a family of single-chip transceivers for T1/E1 and Integrated Distinguishing Features Service Digital Network ISDN primary rate interfaces, operating at 1.544 Mbps or 2.048 Mbps. These devices combine a sophisticated framer, transmit and receive slip ! Single-chip T1/E1 framer with short/long

CX28331

Abstract: CX28332 CX28333 TBR24 48-ETQFP AMI 52 732 V
Contextual Info: Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit Data Sheet CX28331/CX28332/CX28333 –3x 28333-DSH-002-B Feb 2003 Revision History Revision Level Date Description A — 6/2001 Initial Release [Document number 28333-DSH-002-A] B — 2/2003 Removed CX2833i-1x information (see separate document)

jat52

Abstract: TA-TSY-000191 PM5319 PM5319-NI PMC-2030860
Contextual Info: us t, 20 04 09 :2 1: 24 PM ARROW 622 ASSP Telecom Standard Product Data Sheet Released es da y, 10 Au g PM5319 gi es , In c. on Tu ARROW 622 Released Issue No. 2: July 2004 Do wn lo ad ed by Sc o tt E st es of i 2T ec h no lo ASSP Telecom Standard Product Data Sheet

Diode LT 228d

Abstract: 1E2H SMD making code DV5
Contextual Info: 7: 43 AM PM4323 OCTLIU LT Device ASSP Telecom Standard Product Data Sheet Released ,0 ay co n Th ur sd OCTLIU LT 1M ay ,2 00 8 01 :0 PM4323 of Pa rtm in er In Device Telecom Standard Product Proprietary and Confidential Released Issue No. 5: April 2008 Do

LR 4100 RELAY

Contextual Info: 58 AM TE-32 ASSP Telecom Standard Product Data Sheet Released r, 20 05 12 :5 3: PM4332 y, 13 De ce m be TE-32 in er In co n Tu es da High Density 32 Channel T1/E1/J1 Framer Proprietary and Confidential Released Issue No. 6: November 2005 Do wn lo ad ed by

LR 4100 RELAY

Abstract: PM8316PGI 315-B PM8316-PGI
Contextual Info: PM8316 TEMUX 84 RELEASED DATA SHEET ISSUE 9 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX 10 :3 5: 14 PM PMC-1991437 ,1 3M ar ch ,2 00 6 PM8316 co n Mo nd ay TEMUX 84 DATA SHEET Do wn l oa de d by C on te nt T ea m of Pa rtm in er In HIGH DENSITY T1/E1 FRAMER WITH

Contextual Info: DALLAS SEMICONDUCTOR FEATURES • Recovers clock and d a ta o ffo fT I lines from 0 to 6,000 feet in length • +0 to -30dBSX receiver sensitivity • Built-in Automatic Line Build Out ALBO circuitry; no tuning or external components required • Dejitters the recovered clock and data

Contextual Info: DS2190-003 DS2190-003 DALLAS SEM ICONDUCTOR T1 NETWORK INTERFACE UNIT NIU PIN CONNECTIONS FEATURES • Modularized network interface for 1.544 Mbps T1 services • Network side connects directly to T1 line • Compatible with DS2180A Transceiver • Small size-approximately six square inchespermits integration onto line cards

cept lpd d

Contextual Info: DALLAS DS2188 T1/CEPT Jitter Attenuator s e m ic o n d u c to r PIN ASSIGNMENT FEATURES • Attenuates clock and datajitter present inT1 orCEPT lines C 1 16 H VDD RPOS C 2 15 RNEG C 3 14 RCLK C 4 13 C 5 L 6 C 7 C 8 12 D □ H 1 Il D H DJA • Meets the jitter attenuation templates outlined in