ACT118 Search Results

74AC11810

Abstract: 74AC11810D 74AC11810N 74ACT11810 74ACT11810D 74ACT11810N
Contextual Info: Philips Components— Signetics Document No. 853-1513 ECN No. 00732 Date of Issue October 17,1990 Status Product Specification 74AC/ACT11810 Quad 2-input Exclusive-NOR gate ACL P ro d u c ts FEATURES • • • • CMOS AC and TTL (ACT) voltage level inputs

74AC11862

Contextual Info: 74AC/ACT11862 Signetics 10-Wide Transceiver; 3-State; INV Objective Specification ACL Products FEATURES GENERAL INFORMATION • High-speed bus Interface buffering for wide address/data paths or buses carrying parity • Output capability: ±24mA SYMBOL w 'PUL

74AC11874D

Abstract: 74AC11874N 74ACT11874D 74ACT11874N
Contextual Info: Philips Components—Signetics 74AC/ACT11874 Document No. ECN No. Date of issue October 17,1990 Status Preliminary Specification Dual 4-bit D-type edge-triggered flip-flop with clear 3-State ACL Products QUICK REFERENCE DATA FEATURES • 3-S tate output buffers

74ACT11873

Abstract: 74AC11873
Contextual Info: Philips Components—Signetics 74AC/ACT11873 Document No. ECN No. Date of Issue October 1 7 ,1 9 9 0 Status Preliminary Specification Dual 4-bit D-type transparent latch with clear 3-State A C L Prod ucts QUICK REFERENCE DATA FEATURES • 3-State output buffers

Contextual Info: 74AC/ACT11843 Signetics 9-Wide D-Type Transparent Latch with Set and Reset; 3-State Objective Specification ACL Products FEATURES GENERAL INFORMATION • High-speed parallel latches • Extra data width for wide address/ data paths or buses with parity C O N D IT IO N S

74AC11827

Contextual Info: 74AC/ACT11827 Signetics 10-Wide Buffer/Line Driver; 3-State Objective Specification ACL Products GENERAL INFORMATION FEATURES C O N D IT IO N S T . = 25°C; G N D = 0V ; • 3-State buffers • Output capability: ±24 mA • CMOS AC and TTL (ACT) voltage

74AC11825

Abstract: fa 5542
Contextual Info: 74AC/ACT11825 Signetics Octal D-Type Flip-Flop with Reset and Enable; PositiveEdge Trigger; 3-State Objective Specification ACL Products GENERAL INFORMATION FEATURES • High-speed parallel registers with positive edge-triggered D-type flipflops • Output capability: ±24mA

74AC11828

Abstract: 74AC11828D 74AC11828N 74ACT11828 74ACT11828D 74ACT11828N
Contextual Info: P hilips C om ponents— S ignetics 74AC/ACT11828 Document No. ECN No. Date of Issue February 1 9 ,1 9 9 0 Status Preliminary Specification 10-wide buffer/line driver 3-State , INV A C L P ro du cts FEATURES • • QUICK REFERENCE DATA 3-S tate buffers Output capability: ± 2 4 mA

Contextual Info: 74AC/ACT11863 Signetics 9-Wide Transceiver; 3-State Objective Specification ACL Products GENERAL INFORMATION FEATURES • High-speed bus Interface buffering for w ide address/data paths or buses carrying parity SYMBOL , PLH/ 'PHL • Output capability: ±24mA

Contextual Info: Philips Components— Signetics 74AC/ACT11874 Document No. ECN No. Date of Issue October 17,1990 Status Preliminary Specification Dual 4-bit D-type edge-triggered flip-flop with clear 3-State A C L Products QUICK REFERENCE DATA FEATURES • 3-State output buffers

C1055

Contextual Info: 74AC/ACT11826 Signetics O ctal D-Type Flip-Flop with Reset and Enable; PositiveEdge Trigger; 3-State; INV Objective Specification A C L P r o d u c ts G E N E R A L INFORM ATION FEATURES • High-speed parallel registers with positive edge-triggered D-type flipflops

TI0149-D3373

Contextual Info: ACT11827, ACT11827 10-BIT BUFFERS/BUS DRIVERS WITH 3-STATE OUTPUTS TI0149— D3373, NOVEM BER 19B9— REVISED MARCH 1990 ACT11827 . . . JT PACKAGE ACT11827 . . . DW OR NT PACKAGE • Inputs are TTL-Voltage Compatible 3-State Outputs Drive Bus Lines or Buffer

74ACT11181

Contextual Info: 74ACT11181 ARITHMETIC LOGIC UNIT/FUNCTION GENERATOR ą ą SCAS086 − D3200, OCTOBER 1989 − REVISED APRIL 1993 • • • • • • • • DW PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible New Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations

74ACT11181

Contextual Info: 74ACT11181 ARITHMETIC LOGIC UNIT/FUNCTION GENERATOR ą ą SCAS086 − D3200, OCTOBER 1989 − REVISED APRIL 1993 • • • • • • • • DW PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible New Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations

Contextual Info: 74A C / A C T 11810 Quad 2-Input Exclusive-NOR Gate S ig n e tic s I ACL Products FEATURES Preliminary Specification • Output capability: ±24 mA • CMOS AC and TTL (ACT) voltage level Inputs • 50n incident wave switching • Center-pin Vcc and ground con­

74ACT11181

Contextual Info: 74ACT11181 ARITHMETIC LOGIC UNIT/FUNCTION GENERATOR SCAS086 – D3200, OCTOBER 1989 – REVISED APRIL 1993 • • • • • • • • DW PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible New Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations

54ACT11827

Abstract: 74ACT11827
Contextual Info: ACT11827, ACT11827 10ĆBIT BUFFERS/BUS DRIVERS WITH 3ĆSTATE OUTPUTS ą SCAS078 − NOVEMBER 1989 − REVISED APRIL 1993 • • • • • • • ACT11827 . . . JT PACKAGE ACT11827 . . . DW PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible 3-State Outputs Drive Bus Lines or Buffer

Contextual Info: ACT11800, ACT11800 TRIPLE 4–INPUT AND/NAND GATES SCAS245 – JULY 1990 – REVISED AUGUST 1992 • • • • • 1A 1Y 1Z 2Y GND GND GND GND 2Z 3Y 3Z 3D 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 1B 1C 1D 2A 2B VCC VCC 2C 2D 3A

54ACT11833

Abstract: 74ACT11833
Contextual Info: ACT11833, ACT11833 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS D3449. MARCH 1990-REVISED OCTOBER 1990 ACT11833 . . . JT PACKAGE ACT11833 . . . DW OR NT PACKAGE TOP VIEW Inputs are TTL-Voltage Compatible High-Speed Bus Transceivers With Parity Generator/Checker

74ACT11882

Abstract: APLUS 54ACT11881 54ACT11882 74ACT11881 D3480
Contextual Info: ACT11881, ACT11881 ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS D3480, MARCH 1990 ACT11881 . . . JT OR JW PACKAGE ACT11881 . . DW OR NT PACKAGE TOP VIEW Inputs are TTL-Voltage C om patible Full Look-A head fo r High-Speed O perations on Long W ords

54ACT11853

Abstract: 74ACT11853 D3474
Contextual Info: ACT11853, ACT11853 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS D3474, MARCH 1990-REV1SED OCTOBER 1990 ACT11853 . . . JT PACKAGE ACT11853 . . . OW OB NT PACKAGE TOP VIEW High-Speed Bus Transceivers With Parity Generator/Checker Parity-Error-Flag Open-Drain Output

74ACT11181

Contextual Info: 74ACT11181 ARITHMETIC LOGIC UNIT/FUNCTION GENERATOR ą ą SCAS086 − D3200, OCTOBER 1989 − REVISED APRIL 1993 • • • • • • • • DW PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible New Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations

74ACT11181

Contextual Info: 74ACT11181 ARITHMETIC LOGIC UNIT/FUNCTION GENERATOR SCAS086 – D3200, OCTOBER 1989 – REVISED APRIL 1993 • • • • • • • • DW PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible New Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations

74ACT11014

Abstract: 74AC11014 74AC11014D 74AC11014N 74ACT11014D 74ACT11014N AC11014 ACT11014 74ACT11873 74AC11873
Contextual Info: Philips Components—Signetics Document No. 853-1487 ECN No. 00730 Date of Issue O c to b e r 17, 1990 Status Product Specification AC11014 : Product Specification ACT11014 : Objective Specification A C L P ro d u cts QUICK REFERENCE DATA FEATURES • O u tp u t c a p a b ility : ± 2 4 m A