ACTEL A54SX72A TID Search Results

A1010B

Abstract: Actel a54sx72a tid A54SX72A TID
Contextual Info: Actel FPGAs for Aerospace Applications When Failure is not an Option As a leading supplier of high reliability FPGAs, Actel offers programmable logic devices for a variety of high reliability applications ranging from commercial aviation and extreme environments to military

RTSX32SU CQ84

Abstract: RT3PE3000L CQ256 CQFP 256 PIN actel A54SX32A SEU RT3PE600L Cqfp256 RTAX2000 ACTEL CCGA 624 mechanical rtax2000sl aircraft logic gates
Contextual Info: System-Critical FPGAs Product Catalog November 2009 Taking Designs from Earth to Outer Space Whether you’re designing for sea-level or 2,000,000 miles into space, Actel’s high-reliability, low-power FPGAs are your best choice. With a history of providing the most reliable, robust, low-power flash and antifuse-based FPGAs in

QFN108

Abstract: QFN-132 kl1-v1 208 pin rqfp drawing qfn132 RT3PE3000L CQ256 DIMENSIONS pqfp 100 actel package mechanical drawing Actel A40MX04 PBGA 23X23 0.8 pitch
Contextual Info: v 11. 2 Package Mechanical Drawings Ceramic Pin Grid Array 84-Pin CPGA Top View 0.050" ± 0.010" Pin #1 ID 0.045" 0.055" 0.015" 0.018" ± 0.002" 0.100" BSC 1.100" ± 0.020" square 0.072" 0.088" L 0.120" 0.140" Side View K J H G F 1.000" BSC E D C B A 1 2 3

Contextual Info: v2 . 1 RTSX-S RadTolerant FPGAs Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case

ACTEL CCGA 624 mechanical

Abstract: 208-Pin CQFP Actel a54sx72a tid CCGA -CG 472
Contextual Info: v2 . 2 RTSX-S RadTolerant FPGAs Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case

RT54SX72SCQ208

Abstract: Actel a54sx72a tid RT54SX72S matsua fuse resistor PQFP die size actel 1020 datasheet ACTEL CCGA 624 mechanical antifuse A54SX72A CC256
Contextual Info: v2 . 2 RTSX-S RadTolerant FPGAs Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case

ACTEL CCGA 624 mechanical

Contextual Info: v2 . 0 RTSX-S RadTolerant FPGAs Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case

rt54sx32su

Abstract: RTSX72 RTSX32SU RTSX72-S
Contextual Info: Advanced v0.1 RTSX-SU RadTolerant FPGAs UMC u e Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case

RTSX32su

Abstract: RTSX32SU CQ84 RTSX72SU
Contextual Info: v2.0 RTSX-SU RadTolerant FPGAs UMC u e Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case

RTSX32SU

Abstract: RTSX32 PQFP die size C5249 bst r16 166 P790 actel 1020 datasheet A54SX72A CC256 CQ208
Contextual Info: Advanced v0.3 RTSX-SU RadTolerant FPGAs UMC u e Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case

RTSX72

Abstract: RTSX72SU A54SX72A TID "tristate buffer" A54SX32S-PQ208 RT54SXproto
Contextual Info: Advanced v0.2 RTSX-SU RadTolerant FPGAs UMC u e Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case

SU 177

Abstract: RTSX32SU A54SX72* radiation Actel a54sx72a tid antifuse A54SX72A CC256 CG624 CQ208 CQ256
Contextual Info: Advanced v0.3 RTSX-SU RadTolerant FPGAs UMC u e Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case

RTSX32SU

Abstract: RTSX32SU CQ84 rtsx72su RTSX32 RTSX-SU 1/RTSX32su CC256 PRB-1 actel 1020 datasheet CG624
Contextual Info: Revision 7 RTSX-SU RadTolerant FPGAs UMC FuseLock Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case

SMD ARAY

Contextual Info: Revision 6 RTSX-SU RadTolerant FPGAs UMC FuseLock Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case

RTSX32su

Abstract: Actel a54sx72a tid Silicon Sculptor II
Contextual Info: v2.2 RTSX-SU RadTolerant FPGAs UMC u e Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case

RTSX32SU CQ84

Abstract: Silicon Sculptor II RTSX32SU actel 1020
Contextual Info: v2.1 RTSX-SU RadTolerant FPGAs UMC u e Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case

RTSX32SU

Abstract: RTSX32SU CQ84 Actel a54sx72a tid RTSX72SU RTSX-SU actel 1020 Silicon Sculptor II actel 1020 datasheet RT54SX E11213
Contextual Info: v2.2 RTSX-SU RadTolerant FPGAs UMC u e Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case

A54SX72* radiation

Abstract: cg624 A54SX72A actel 1020 datasheet RT54SX72S RT54SX-S TM1019 HiRel a54sx72a unused
Contextual Info: Advanced v1.4 RT54SX-S RadTolerant FPGAs for Space Applications S p ec i a l F e a tu r es fo r S p ac e • First Actel FPGA Designed Specifically for Space Applications • Up to 2,012 SEU Hardened Flip-Flops Eliminate Software TMR Necessity LET th > 40, GEO SEU Rate < 10–10

HiRel a54sx72a unused

Contextual Info: Advanced v1.3 RT54SX-S RadTolerant FPGAs for Space Applications Sp e ci a l F ea t ur es f o r Sp a ce • First Actel FPGA Designed Specifically for Space Applications • Up to 2,012 SEU Hardened Flip-Flops Eliminate Software TMR Necessity LET th > 40, GEO SEU Rate < 10–10

HiRel a54sx72a unused

Contextual Info: Advanced v1.6 RTSX-S RadTolerant FPGAs for Space Application S p ec i a l F e a tu r es fo r S p ac e • First Actel FPGA Designed Specifically for Space Applications • Up to 2,012 SEU Hardened Flip-Flops Eliminate Software TMR Necessity LET th > 40, GEO SEU Rate < 10–10

HiRel a54sx72a unused

Contextual Info: Advanced v1.5 RTSX-S RadTolerant FPGAs for Space Applications Sp e ci a l F ea t ur es f o r Sp a ce • First Actel FPGA Designed Specifically for Space Applications • Up to 2,012 SEU Hardened Flip-Flops Eliminate Software TMR Necessity LET th > 40, GEO SEU Rate < 10–10

RTSX32SU CQ84 PROTO

Abstract: CQ84 SOC 8A fuse smd RTSX32SU CQ84 rtsx72su RTSX32SU CG624 thermal expansion
Contextual Info: Revision 8 RTSX-SU Radiation-Tolerant FPGAs UMC Designed for Space • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single Event Upsets (SEU) to LETth > 40 MeVcm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case

RTSX32SU CQ84 PROTO

Abstract: RTSX32SU CQ84 RTSX72SU1 SOC 8A fuse smd RTSX32su CG624 thermal expansion
Contextual Info: Revision 9 RTSX-SU Radiation-Tolerant FPGAs UMC Designed for Space • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single Event Upsets (SEU) to LETth > 40 MeVcm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case