AD T004 Search Results

628F

Abstract: MAX714
Contextual Info: IS28F400BV/BLV 262,144 x 16/524,288 x 8 SmartVoltage BOOT BLOCK FLASH MEMORY AD VA N C E INFORM ATIO N DEC EM B ER 1996 • SmartVoltage Technology — 5V or 12V Program/Erase — 2.7V, 3.3V or 5V Read Operation • Industrial Temperature Operation 40°C to +85° C

amplitude modulator gilbert cell

Abstract: irf2703 modulation demodulation ssb circuit ssb demodulator ic 630S2 RF2703 S1260 SSB Modulator application note 1260F tdq4
Contextual Info: RF2703 MICRO-DEVICES Q U AD RATU RE M 0D U LA T0 R ;D E M 0 D U LA T0 R Typ ical A p plicatio ns • Digital and Analog Receivers and Transmitters Spread Spectrum Communication Systems Interactive Cable Systems • High Data Rate Digital Communications Portable Battery Powered Equipment

diode GFP AA

Abstract: KT 208 sierra The SDH interface in AXE MQE vco ss19 810 DD107* CONVERTER WD 969 TAA 611 T12 ic tb 810 datasheet hp 9720
Contextual Info: D A TA S H E E T PM PM C -970133 IS S U E 2 n /K PR ELIM INA R Y 1 PMC-Sierra, Inc. PM5342 s p e c tra -155 SO N ET/SDH PA YLO AD EXTRACTO R/ALIG NER FEATURES • Monolithic SONET/SDH PAYLOAD EXTRACTOR/ALIGNER for use in STS-1 STM-0/AU3 , STS-3 (STM-1/AU3) or STS-3c (STM-1/AU4) interface

Contextual Info: tape and reel packaging for surface mount devices Design-For-Assembly DFA a n d Design-For-Manufacture (DFM) stand tall alongside C AD /C AM in the quest to optimize profitabil­ ity, prod uction efficie n cy and e q u ip m e n t o p erating usage. A utom ation o f surface-m ount assembly by th e use o f pick-andp la ce equ ipm ent to handle tiny com ponents has been e n h a n ce d

Contextual Info: STARTECH ST68C454 A n 3S? E X 4 R C o m p a n y Printed August 3,1995 QUAD ASYNCHRONOUS RECEIVER AND TRANSMITTER DESCRIPTION PLCC Package The ST68C454 is a quad universal asynchronous receiver and transmitter with modem control signals. D e sig n e d to in te rfa c e w ith M O T O R O L A ,

Contextual Info: IS 4 2 S 1 6 1 0 0 512K Words x 16 Bits x 2 Banks 16-MBIT SYNCHRONOUS DYNAMIC RAM ISSI ADVANCE INFORMATION SEPTEMBER 1998 DESCRIPTION FEATURES Clock frequency: 100 MHz Fully synchronous; all signals referenced to a positive clock edge Two banks can be operated simultaneously and

qml-38535

Abstract: SMD a34 PA84M QML-38534 5962-XXXXXZZ
Contextual Info: 07^ SE * U S •SOVMNMIM» WMNTING OWICI: 19«7 — 74».1J9/60»11 87 D IS T R IB U T IO N S T A T E M E N T A. 5962-E275 A pproved for p u b lic rele a s e ; d is trib u tio n Is un lim ited. ■ T00470fl 002bB7b MS5 ■ 1. SCOPE 1.1 Scope. This drawing forms a part of a one part - one part number documentation system see 6.6

ST16C654

Abstract: 16c654
Contextual Info: \ Preliminary \ / Information J STARTECH ST16C654 Printed August 3,1995 An X * EX4R Company QUAD UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER WITH 64 BYTES OF FIFO AND INFRARED ENCODER/DECODER DESCRIPTION PLCC Package The ST16C654 is a Quad universal asynchronous

A42 B331

Abstract: CA91C860B-40IQ CA91C860B-40CQ CA91C860B-50CQ tea 1601 t CA91C860B a44 b331 CA91C860 T337A CA91L860B-50CE
Contextual Info: QSpan CA91C860B, CA91L860B PCI to Motorola Processor Bridge Manual http://www.tundra.com The information in this document is subject to change without notice and should not be construed as a commitment by Tundra Semiconductor Corporation. While reasonable precautions have been taken, Tundra

Contextual Info: PM D a ta s h e e t I PMC-931127 ISSUE 5 1. •V P M C -S ierra, Inc. IV-_ PM7375LASAR-155 LOCAL A m SAR&PHYSICAL LAYER FEATURES • Single-chip Peripheral Component Interface PCI Bus Local ATM Network Interface using SONET/SDH framing at 155.52 or 51.84 Mbit/s and ATM

686 ami bios

Abstract: ami bios 686 RF DELAY LINE 4.3GH A1m anode BZT 030 SARS 03 star delta FORWARD / REVERSE WIRING CONNECTION PX334 845 Mother board Diagram cops instrument display
Contextual Info: S TANDARD PRODUCT PMC-Sierra, Inc. ISSUE 3 P M 7 3 7 5 LASAR-155 LOCAL ATM SAR & PHYSICAL LA YER 1. FEA TU R ES • Single-chip Peripheral Component Interface PCI Bus Local ATM Network Interface using SONET/SDH framing at 155.52 or 51.84 Mbit/s and ATM Adaptation Layer 5 (AAL-5).

Contextual Info: •iOONSna 0 0 0 0 0 4 7 V960PBC V 313 Rev. B1 LOCAL BUS TO PCI BRIDGE FOR i960 Sx PROCESSORS “ • Glueless interface between ¡960Sx processors and the PCI bus • Large, 576-byte FIFOs using V3’s unique D y n a m ic B a n d w id t h A l l o c a t i o n architecture

V96SSC25LP

Contextual Info: ‘ÌOOMEOO 0 0 0 0 3 0 3 ISA V96SSC • * * ▼ / Rev. BO HIGH-INTEGRATION SYSTEM CONTROLLER FOR ¡960 Sx/Jx AND PowerPC 401 Gx PROCESSORS • Direct interface to ¡960Sx/Jx and PPC401Gx processors • High-performance burst DRAM controller • Two-channel fly-by DMA controller

2T312A

Abstract: CA91C860B t413c QSpan t009 t418 T415I ad t004 t313d AD T006
Contextual Info: QSpan II User Manual 8091862_MA001_08 November 2009 6024 Silver Creek Valley Road, San Jose, California 95138 Telephone: 800 345-7015 • (408) 284-8200 • FAX: (408) 284-2775 Printed in U.S.A. 2009 Integrated Device Technology, Inc. GENERAL DISCLAIMER

qspan top mark

Abstract: TIP177 CA91L862A-50IE t415i
Contextual Info: QSpan II CA91L862A PCI to Motorola Processor Bridge Manual www.tundra.com The information in this document is subject to change without notice and should not be construed as a commitment by Tundra Semiconductor Corporation. While reasonable precautions have been taken, Tundra Semiconductor Corporation assumes no

JD 1801 PIN DIAGRAM

Abstract: RTCO Z511A epoch t14 12D1C-D ET 723 TAIS SOT TA-NWT-000253 s004152 0Q0043
Contextual Info: SOT-1 Device SONET STS-1 Overhead Terminator TXC-03001 DATA SHEET Preliminary FEATURES DESCRIPTION Provides SONET interface to any type of payload = The SOT-1 SONET/STS-1 Overhead Terminator per­ forms section, line and path overhead processing for STS-1 SONET signals. This versatile device can be

Contextual Info: ^004200 □□□□102 MST • V961PBC •" V Rev. B1 LOCAL BUS TO PCI BRIDGE FOR i960 Jx AND PowerPC 401 Gx PROCESSORS " • Glueless interface between ¡960Jx, PPC401 Gx processors and the PCI bus • Large, 576-byte FIFOs using V3's unique D y n a m ic B a n d w id t h A l l o c a t i o n ™ architecture

PJ3N

Contextual Info: . . y lf • * ▼ • =1004200 0 0 0 0 0 2 1 V96DPC f « 450 ■ Rev. B1 LOCAL BUS TO PCI BRIDGE FOR i960 Cx/Hx/Jx/Sx AND PowerPC 40lGx PROCESSORS • Glueless interface between i960Sx/Jx/Cx/Hx, PPC401 Gx processors and two PCI buses • On-the-fly byte order endian conversion

logos 4012B

Abstract: 1LB553 Rauland ETS-003 Silec Semiconductors MCP 7833 4057A transistor sr52 74c912 1TK552 74S485
Contextual Info: L p i > « , * S E m Ic O N VOLUM E 3 INTERNATIONAL INTEGRATED CIRCUITS INDEX 5th EDITION 1985 Revised June 1985 COMPILED AND PUBLISHED BY S E M IC O N IN D E X E S L IM IT E D THE SEMICON INDEX SERIES CONSISTS OF VOLUME 1 TRANSISTOR INDEX VOLUME 2 DIODE & SCR INDEX

Viper L2A

Abstract: opti 82c596 82C558N 82C465MV opti 82C556
Contextual Info: 82C556/82C557/82C558N Viper Notebook Chipset Data Book Revision: 1.0 912-3000-032 May 25,199 5 Copyright Copyright 1995, OPTi Inc. All rights reserved. No part of this publication may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language or computer language, in any form or by any means, electronic, mechani­

82C556M

Abstract: OCH168 82C557M 82C558 OPTi 82C546 82c556 CI VIPER 17H 82C558M opti 82c556 IBM motherboard schematics
Contextual Info: twain 82C556M/82C557M/82C558M Viper-M Multimedia Chipset Preliminary Data Book Revision: 1.0 912-2000-010 April 1995 • RODm ^b □ Powered by ICminer.com Electronic-Library Service CopyRight 2003 038 Copyright Copyright 1995, OPTi Inc. All rights reserved. No part of this publication may be reproduced, transmitted, transcribed, stored

3161

Abstract: IS22C111P IS22C111S IS22C111X "Piezo Buzzer" sbt
Contextual Info: ESI' 8 to 12 SEC VOICE ROM ADVANCE INFORMATION FEBRUARY 1997 FEATURES • Voice length at: - 8 KHz sampling is 8 seconds - 6 KHz sampling is 10 seconds - 5 KHz sampling is 12.8 seconds • Silence compression saves memory • Four trigger pins, S1 to S4 for eight sections

Contextual Info: SOT-1 Device SONET STS-1 Overhead Terminator TXC-03001 DATA SHEET Prelim inary DESCRIPTION - -= -• = The SOT-1 SONET/STS-1 Overhead Terminator per­ forms section, line and path overhead processing for STS-1 SONET signals. This versatile device can be

82C568

Abstract: 82C567 4464 64k dram 4464 dram HA20C md4203 AD7166 82C566 SiS chipset 486 opti 82c
Contextual Info: 82C566/82C567/82C568 Viper-MAX Chipset Scaleable MultiMedia PC Solution 1.0 Features CPU Interface • Fully supports all Intel 3.3V Pentium processors P54C™, P55C™, P55CT™ at 50, 60, and 66.667MHz • Supports AMD® K86™ and Cyrix® 6x86 processors