ALTERA SAM Search Results

DDR PHY ASIC

Abstract: ddr ram memory ic CP-01024-1 FLEX10K DDR2-800
Contextual Info: DesignCon 2007 Calibration Techniques for HighBandwidth Source-Synchronous Interfaces Manoj Roge, Altera Corporation Andy Bellis, Altera Corporation Phil Clarke, Altera Corporation Joseph Huang, Altera Corporation Mike Chu, Altera Corporation Yan Chong, Altera Corporation

VR 10K preset

Abstract: Signal Path Designer
Contextual Info: DesignCon 2008 A Reset Control Apparatus for PLL Power-Up Sequence and Auto-Synchronization Kazi Asaduzzaman, Altera Corporation Tim Hoang, Altera Corporation Kang-Wei Lai, Altera Corporation Wanli Chang, Altera Corporation Leon Zheng, Altera Corporation Mian Smith, Altera Corporation

9524 pc

Abstract: cp-01035 IC K140 90 nm hspice
Contextual Info: DesignCon 2008 A Fast Algorithm to Instantly Predict FPGA SSN for Various I/O Pin Assignments Geping Liu, Altera Corporation [gliu@altera.com] Zhuyuan Liu, Altera Corporation Kundan Chand, Altera Corporation San Wong, Altera Corporation Kaiyu Ren, Altera Corporation

leon3

Abstract: processors hardware report ALTERA FPGA
Contextual Info: Altera Innovate Nordic 2007: Leon3 MP on Altera FPGA, Final Report Altera Innovate Nordic 2007 Final Project Report 8/28/2007 1 Altera Innovate Nordic 2007: Leon3 MP on Altera FPGA, Final Report Project name: Leon3 MP on Altera FPGA Team name: Team Hervanta

LMS adaptive filter model for FPGA

Abstract: hyperlynx 90 nm hspice FIR filter matlaB design altera digital graphic equalizer ic LMS matlab CP-01025-1
Contextual Info: Equalization Challenges for 6-Gbps Transceivers Addressed by PELE—A Software-Focused Solution! Tina Tran, Altera Corporation Gary Pratt, Mentor Graphics Corporation Kazi Asaduzzaman, Altera Corporation Mei Luo, Altera Corporation Simar Maangat, Altera Corporation

F487 transistor

Abstract: 2A86 transistor D889 65e9 4B71 65e9 transistor ix 2933 F487 529B 0674
Contextual Info: Altera Software Installation and Licensing Version 10.0 Altera Software Installation and Licensing Version 10.0 Altera Corporation 101 Innovation Drive San Jose, CA 95134 408 544-7000 www.altera.com Altera Software Installation and Licensing Version 10.0

351nF DesignCon 2010 Analysis FPGA Noise Propagation Package Modeling Altera Corporation

Abstract: 400um XCItepi powersi 50GHZ 351nF Design Seminar Signal Transmission Fabrication process steps metal core pcb
Contextual Info: DesignCon 2010 Analysis of FPGA PDN Noise Propagation by Die & Package 3D Modeling Zhe Li, Altera Corporation ZLI@altera.com Dr. Hong Shi, Altera Corporation hshi@altera.com Kenneth Kwan, Altera Corporation kkwan@altera.com Dr. John Y. Xie, Altera Corporation

pll 02 a

Abstract: 800E-02 finite state machine frequency detection using FPGA
Contextual Info: DesignCon 2009 Method and Apparatus of Continuous PLL Adaptation to Variable Reference Input Frequency Tim Hoang, Altera Corporation Sergey Shumarayev, Altera Corporation Kazi Asaduzzaman, Altera Corporation Leon Zheng, Altera Corporation CP-01051-1.0 February 2009

b548

Abstract: d67b datasheet mb 8719 3BA6 3C37 altera jtag ethernet b824 B824 transistor D896 d975
Contextual Info: Altera Software Installation and Licensing Version 9.1 Altera Software Installation and Licensing Version 9.1 Altera Corporation 101 Innovation Drive San Jose, CA 95134 408 544-7000 www.altera.com Altera Software Installation and Licensing Version 9.1

altera de1

Abstract: vhdl code for codec WM8731 music keyboard encoder schematic UART using VHDL rs232 driver Altera Cyclone II 2C20 FPGA Board VHDL audio de1 Altera DE1 Board Using Cyclone II FPGA Circuit WM8731 Altera II 2C20 FPGA verilog code for codec WM8731
Contextual Info: Altera DE1 Board DE1 Development and Education Board User Manual Version 1.1 Copyright 2006 Altera Corporation Altera DE1 Board CONTENTS Chapter 1 DE1

interlaken rtl

Abstract: gearbox rev 10 Gbps ethernet phy analog devices select guide 2010 AN320 CRC32 IP-10GBASERPCS xaui xgmii ip core altera interlaken PHY interface for PCI EXPRESS
Contextual Info: Altera Transceiver PHY IP Core User Guide Altera Transceiver PHY IP Core User Guide 101 Innovation Drive San Jose, CA 95134 www.altera.com UG-01080-1.0 Subscribe Copyright 2010 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, and specific device designations

SCHEMATIC USB to VGA

Abstract: schematic diagram video converter rca to vga vhdl code for codec WM8731 3 digit seven segment 11 pin display schematic diagram vga to tv pin configuration of seven segment usb video player circuit diagram
Contextual Info: Altera DE2 Board DE2 Development and Education Board User Manual Version 1.5 Copyright 2012 Altera Corporation Altera DE2 Board CONTENTS Chapter 1 DE2

INTERPOLATOR 6 BITS SIN COS DATA CLK

Abstract: CP-01066-1 altera 48 fpga
Contextual Info: DesignCon 2010 An On-Die Scope Based on a 40-nm Process FPGA Transceiver Weichi Ding, Altera Corporation Email: weding@altera.com Mingde Pan, Altera Corporation Email: mpan@altera.com Tina Tran, Altera Corporation Email: ttran@altera.com Wilson Wong, Altera Corporation

MegaCore IP Library

Abstract: megacore ip
Contextual Info: OpenCore Plus Evaluation of Megafunctions Application Note 320 November 2007, version 1.6 Introduction Altera and Altera Megafunction Partners Program AMPPSM partners offer a broad portfolio of megafunctions optimized for Altera devices. The Altera MegaCore® functions and AMPP megafunctions are reusable

altddio_out

Abstract: altera double data rate megafunction altddio_in
Contextual Info: Altera Double Data Rate Megafunctions User Guide 101 Innovation Drive San Jose, CA 95134 408 544-7000 http://www.altera.com Quartus II Version: Document Version: Document Date: 2.2 1.0 May 2003 Copyright Altera Double Data Rate Megafunctions User Guide Copyright 2003 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo,

"Constant fraction discriminator"

Abstract: cti pet Constant fraction discriminator SIEMENS BST vhdl cordic code EPC1064V HP 30 pin lcd flex cable pinout vhdl code for cordic Constant fraction timing discriminator EPF10K50EQI240-2
Contextual Info: & News Views First Quarter, February 2000 The Programmable Solutions Company Newsletter for Altera Customers Altera Provides World-Class HDL Synthesis & Simulation Tools Altera has entered into agreements with Synopsys, Inc., and Mentor Graphics Corporation that enable Altera’s entire

vhdl code for lcd display for DE2 altera

Abstract: mp3 altera de2 board altera de2 board sd card VHDL audio codec ON DE2 altera de2 board vga connector de2 altera Schematic LED panel display tv de2 video image processing altera vhdl code for rs232 receiver altera schematic diagram pc vga to tv rca converter
Contextual Info: Altera DE2 Board DE2 Development and Education Board User Manual Version 1.42 Copyright 2008 Altera Corporation Altera DE2 Board CONTENTS Chapter 1 DE2

Contextual Info: Early SSN Estimator User Guide for Altera Programmable Devices 101 Innovation Drive San Jose, CA 95134 www.altera.com Document Version: Document Date: 1.0 November 2009 Copyright © 2009 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other

hdmi SDI

Abstract: PC48F4400P0VB00 Si570 gx d-vda led full color screen fpga schematic usb to lan cable adapter USB 2.0 SPI Flash Programmer schematic LT2418
Contextual Info: Audio Video Development Kit, Stratix IV GX Edition User Guide 101 Innovation Drive San Jose, CA 95134 www.altera.com UG-01066-2.0 November 2009 Altera Corporation Based on Altera Complete Design Suite version 9.1 Copyright © 2009 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the

ieee floating point vhdl

Abstract: verilog code for single precision floating point multiplication ieee floating point multiplier vhdl object counter project report to download AN391 EP3C120 vhdl code for floating point multiplier
Contextual Info: Using Nios II Floating-Point Custom Instructions Tutorial 101 Innovation Drive San Jose, CA 95134 www.altera.com TU-N2FLTNGPNT-2.0 Copyright 2010 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, and specific device designations are trademarks and/or service marks of Altera Corporation

8257D

Abstract: 81134A E4440A UFX9836 pll 02 a SANWO 8131a Noisecom UFX
Contextual Info: DesignCon 2008 A Jitter Estimation Method for Cascaded, Programmable PhaseLocked Loops Daniel Chow, Altera Corporation dchow@altera.com Vincent Tsui, Altera Corporation vtsui@altera.com San Wong, Altera Corporation sanwong@altera.com CP-01036-1.0 February 2008

electrical engineering projects

Abstract: "toan nguyen" 90 nm CMOS CLK180 PRBS23 TSMC 40nm 32nm tsmc TSMC 90nm TSMC 40nm layout issue
Contextual Info: DesignCon 2008 Using Programmable Logic for Receiver Offset and Yield Enhancement Simar Maangat, Altera Corporation Email: smaangat@altera.com Toan Nguyen, Altera Corporation Email: tonguyen@altera.com Wilson Wong, Altera Corporation Email: wwong@altera.com

Contextual Info: Altera Software Installation and Licensing Subscribe Send Feedback MNL-1065 2013.11.04 101 Innovation Drive San Jose, CA 95134 www.altera.com TOC-2 Altera Software Installation and Licensing Contents Altera Software Installation and

32x32 DDR2 SDRAM circuit diagram

Abstract: 32x32 DDR2 SDRAM circuit ddr2 ram pcie Design guide AN-431-1
Contextual Info: PCI Express-to-DDR2 SDRAM Reference Design Application Note 431 August 2006, ver. 1.0 Introduction The Altera PCI Express-to-DDR2 SDRAM reference design provides a sample interface between the Altera PCI Express MegaCore® function and a 64-bit, 256-MByte DDR2 SDRAM memory. Altera offers this