AMBA BIDIRECTIONAL BUS Search Results

AMBA BIDIRECTIONAL BUS Result Highlights (5)

Part	Manufacturer	Description
TC7MP3125FT	Toshiba Electronic Devices & Storage Corporation	Level shifter, Bidirectional, 2-Bit x 2 Dual Supply Bus Transceiver, TSSOP16B, -40 to 85 degC
DF2B20M4SL	Toshiba Electronic Devices & Storage Corporation	TVS Diode (ESD Protection Diode), Bidirectional, +/-18.5 V, SOD-962 (SL2)
DF2B6M4ASL	Toshiba Electronic Devices & Storage Corporation	TVS Diode (ESD Protection Diode), Bidirectional, +/-5.5 V, SOD-962 (SL2)
DF2B7BSL	Toshiba Electronic Devices & Storage Corporation	TVS Diode (ESD Protection Diode), Bidirectional, +/-5.5 V, SOD-962 (SL2)
DF2B7ASL	Toshiba Electronic Devices & Storage Corporation	TVS Diode (ESD Protection Diode), Bidirectional, +/-5.5 V, SOD-962 (SL2)

AMBA BIDIRECTIONAL BUS Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
APB to I2C interface Abstract: i2c controller with apb interface AMBA APB bus protocol vhdl i2c DB-I2C-M-APB complete I2C specifications verilog program for 16 bit processor verilog ARC processor i2c/APB to I2C interface Contextual Info: Digital Blocks DB-I2C-M-APB Semiconductor IP APB Bus I2C Controller General Description The Digital Blocks DB-I2C-M-APB Controller IP Core interfaces an ARM, MIPS, PowerPC, ARC, or other high performance microprocessor via the AMBA 2.0 APB System Interconnect Fabric to an I2C Bus. The I2C is a two-wire bidirectional interface	Original		PDF
ARM Advanced RISC Machine Abstract: AMBA Peripheral Bus decoder Advanced RISC Machine Advanced RISC Machines AMBA peripheral Contextual Info: AMBA Peripheral Bus Controller Data Sheet Copyright 1997 Advanced RISC Machines Ltd ARM . All rights reserved. ARM DDI 0044C AMBA Peripheral Bus Controller Data Sheet Copyright © 1997 Advanced RISC Machines Ltd (ARM). All rights reserved. Release Information	Original	0044C ARM Advanced RISC Machine AMBA Peripheral Bus decoder Advanced RISC Machine Advanced RISC Machines AMBA peripheral	PDF
verilog code for amba ahb bus Abstract: verilog code AMBA AHB verilog code for amba ahb master ahb slave verilog code verilog code for i2s bus ahb wrapper verilog code verilog code for ahb bus slave ahb slave RTL verilog i2s amba ahb verilog code Contextual Info: I2S core meets the Philips InterIC Sound bus specification Supports Master/Slave and Receiver/Transmitter modes I2S-AHB Eight configurable stereo channels Inter-IC Sound Bus Core for AMBA AHB Data mode capabilities: 22.05, 24; 32, 44.1; 48; 88.2; 96; 176.4; 192kHz	Original	192kHz verilog code for amba ahb bus verilog code AMBA AHB verilog code for amba ahb master ahb slave verilog code verilog code for i2s bus ahb wrapper verilog code verilog code for ahb bus slave ahb slave RTL verilog i2s amba ahb verilog code	PDF
IEEE1284 Abstract: parallel port interface "parallel port interface" IEEE-1284 Contextual Info: AMBA IEEE1284 Parallel Port Interface Data Sheet Copyright 1997 ARM Limited. All rights reserved. ARM DDI 0083A AMBA IEEE1284 Parallel Port Interface Data Sheet Copyright © 1997 ARM Limited. All rights reserved. Release Information Change history Date	Original	IEEE1284 parallel port interface "parallel port interface" IEEE-1284	PDF
AMBA APB Abstract: AMBA APB bus Contextual Info: Features SOC-GPIO-APB General Purpose I/O Core  Configurable I/O lines  Scalable  Interrupt output  Selectable level sensitive or edge triggered interrupt system  Supports asynchronous inputs  AMBA APB bus interface The SOC-GPIO-APB is a configurable AMBA APB General Purpose I/O core. The	Original		PDF
AMBA Abstract: tic 32 47LF 6B75 tic 131 Contextual Info: AMBA Test Interface Controller Data Sheet Copyright 1995-1997 ARM Limited. All rights reserved. DDI 0043E AMBA Test Interface Controller Data Sheet Copyright © 1995-1997 ARM Limited. All rights reserved. Release Information The following changes have been made to this book.	Original	0043E AMBA tic 32 47LF 6B75 tic 131	PDF
PWM DC-DC ARM Abstract: AMBA Peripheral Bus decoder Contextual Info: ARM PrimeCell DC-DC Converter Interface PL160 Technical Reference Manual ARM DDI 0147D ARM PrimeCell™ DC-DC Converter Interface (PL160) Technical Reference Manual Copyright ARM Limited 1999. All rights reserved. Release information Change history	Original	PL160) 0147D PWM DC-DC ARM AMBA Peripheral Bus decoder	PDF
AMBA APB UART Abstract: atmel 018 AT697 AT697E pinout socket 754 D1313 sparc v8 SPARC v8 architecture BLOCK DIAGRAM D22A Contextual Info: Features • SPARC V8 High Performance Low-power 32-bit Architecture • • • • • • • • • • • • • – LEON2-FT 1.0.13 compliant – 8 Register Windows Advanced Architecture: – On-chip Amba Bus – 5 Stage Pipeline – 16 kbyte Multi-sets Data Cache	Original	32-bit 24-bit 33MHz 32/64-bit 4226BS AMBA APB UART atmel 018 AT697 AT697E pinout socket 754 D1313 sparc v8 SPARC v8 architecture BLOCK DIAGRAM D22A	PDF
AMBA 3.0 technical reference manual Abstract: amba apb verilog coding AMBA 3.0 technical summary vhdl code for amba 28F160F3 28F800F3 KM681002A static memory controller AMBA Peripheral Bus decoder Contextual Info: AMBA ASB Peripheral Static Memory Controller PL091 Technical Reference Manual DDI 0167A AMBA™ ASB SMC (PL091) Technical Reference Manual Copyright ARM Limited 1999. All rights reserved. Release information Change history Date Issue Change July 1999	Original	PL091) AMBA 3.0 technical reference manual amba apb verilog coding AMBA 3.0 technical summary vhdl code for amba 28F160F3 28F800F3 KM681002A static memory controller AMBA Peripheral Bus decoder	PDF
Basic ARM7tdmi block diagram Abstract: ARM7tdmi coprocessor 0045D Contextual Info: AMBA ARM7TDMI Interface Data Sheet Copyright 1995-1997 ARM Limited. All rights reserved. ARM DDI 0045D AMBA ARM7TDMI Interface Data Sheet Copyright © 1995-1997 ARM Limited. All rights reserved. Release Information The following changes have been made to this document.	Original	0045D Basic ARM7tdmi block diagram ARM7tdmi coprocessor 0045D	PDF
AMBA Abstract: DDI0052C IHI-0001 Contextual Info: AMBA Static Memory Interface Data Sheet Copyright 1997 ARM limited. All rights reserved. ARM DDI0052C AMBA Static Memory Interface Data Sheet Copyright © 1997 ARM limited. All rights reserved. Release Information Change history Date Issue Change December 1995	Original	DDI0052C 128Kb 32-bit 16Kx32-bit AMBA DDI0052C IHI-0001	PDF
0005A Abstract: IHI-0001 Contextual Info: AMBA Interconnection Schemes Application Note 05 ARM DAI 0005A AMBA Interconnection Schemes Application Note 05 Copyright ARM Limited 1998. All rights reserved. Release information Change history Description Issue Change November 1998 A First release Proprietary notice	Original		PDF
PS2 keyboard PROTOCOL Abstract: PL050 PL05 ps2 keyboard 0143C ibm ps2 ps2 keyboard interface scan Contextual Info: ARM PrimeCell PS2 Keyboard/Mouse Interface PL050 Technical Reference Manual DDI 0143C ARM PrimeCell™ PS2 Keyboard/Mouse Interface (PL050) Technical Reference Manual Copyright ARM Limited 1999. All rights reserved. Release information Change history	Original	PL050) 0143C PS2 keyboard PROTOCOL PL050 PL05 ps2 keyboard 0143C ibm ps2 ps2 keyboard interface scan	PDF
80C552 i2c Abstract: 80C552 "programmable clock" i2c I2C master controller code I2C CODE OF READ IN V HDL I2c core implementation Contextual Info: I2C Master/Slave Bus Controller Core The I2C core implements a serial interface that meets the Philips I2C bus specification and supports all transfer modes from and to the I2C bus. The I2C logic handles bytes transfer autonomously. It also keeps track of serial transfers, and a status register i2csta reflects the status of I2C Bus Controller and the I2C	Original		PDF

Contextual Info:  Compliant with PCI Express Base Specification 1.1  Implements Transaction, Data CPXP-EPx8 PCI Express Endpoint Controller Megafunction with SoC Bridge Extensions for AMBA AXI Link, and Physical protocol layers in hardware  Supports x8 link width	Original		PDF
AMBA APB UART Abstract: AT697E SPARC v8 architecture BLOCK DIAGRAM 0.18 um CMOS Contextual Info: Features • SPARC V8 High-performance Low-power 32-bit Architecture – 8 Register Windows • Integrated 32/64-bit Floating Point Unit • Advanced Architecture • • • • • • • • • • • • – On-chip AMBA Bus – 5-stage Pipeline – 16-Kbyte Multi-sets Data Cache	Original	32-bit 32/64-bit 16-Kbyte 32-Kbyte 24-bit 4226AS AMBA APB UART AT697E SPARC v8 architecture BLOCK DIAGRAM 0.18 um CMOS	PDF
TSMC 0.18Um Abstract: TSMC 0.13um process specification 80C552 TSMC 90nm Contextual Info: Uses two wires to transfer information between devices o Serial Clock Line SCL SCL I2CS Slave Bus Controller Core The I2CS Bus Controller logic provides a serial interface that meets the Philips I2C bus specification and supports all slave transfer modes to and from the I2C bus. The I2CS	Original		PDF
80C552 Abstract: 80C552 interfacing Contextual Info: Uses two wires to transfer information between devices o Serial Clock Line SCL SCL I2CS Slave Bus Controller Core The I2CS Bus Controller logic provides a serial interface that meets the Philips I2C bus specification and supports all slave transfer modes to and from the I2C bus. The I2CS	Original		PDF
AMBA peripheral Contextual Info: AMBA Timer Data Sheet Copyright 1995-1997 ARM Limited. All rights reserved. ARM DDI 0049C AMBA Timer Data Sheet Copyright © 1995-1997 ARM Limited. All rights reserved. Release Information The following changes have been made to this book. Change History	Original	0049C 16-bit AMBA peripheral	PDF
80C552 Contextual Info: Uses two wires to transfer information between devices o Serial Clock Line SCL SCL I2CS Slave Bus Controller Megafunction The I2CS Bus Controller logic provides a serial interface that meets the Philips I2C bus specification and supports all slave transfer modes to and from the I2C bus. The I2CS	Original	EP1S10-5 80C552	PDF
Contextual Info: Compliant with PCI Express Base Specification 1.1 CPXP-EPx8 PCI Express Endpoint Controller Core with SoC Bridge Extensions for AMBA AXI Implements a PCI Express endpoint controller that is compliant with PCI Express Base specification 1.1, including the Transaction, Data Link, and Physical protocol layers. It	Original		PDF
nvidia application notes Abstract: 5VLX330-1 Contextual Info:  Compliant with PCI Express Base Specification 1.1  Implements Transaction, Data CPXP-EPx8 PCI Express Endpoint Controller Core with SoC Bridge Extensions for AMBA AXI Link, and Physical protocol layers in hardware  Supports x8 link width  Offers a data rate of 2.5 Gbps	Original		PDF
AMBA apb memory controller Abstract: reset map Contextual Info: AMBA Remap and Pause Revision: r0p0 Technical Reference Manual Copyright 1997 ARM Limited. All rights reserved. ARM DDI 0048AC AMBA Remap and Pause Technical Reference Manual Copyright © 1997 ARM Limited. All rights reserved. Release Information The following changes have been made to this book.	Original	0048AC AMBA apb memory controller reset map	PDF
AMBA APB bus protocol Abstract: spi bus arbiter IHI-0001 Contextual Info: Green AMBA Peripherals Technical Manual Order Number C14058 This document contains proprietary information of LSI Logic Corporation. The information contained herein is not to be used by or disclosed to third parties without the express written permission of an officer of LSI Logic Corporation.	Original	C14058 DB14-000047-00, AMBA APB bus protocol spi bus arbiter IHI-0001	PDF

AMBA BIDIRECTIONAL BUS Search Results

AMBA BIDIRECTIONAL BUS Result Highlights (5)

AMBA BIDIRECTIONAL BUS Datasheets Context Search

APB to I2C interface

ARM Advanced RISC Machine

verilog code for amba ahb bus

IEEE1284

AMBA APB

AMBA

PWM DC-DC ARM

AMBA APB UART

AMBA 3.0 technical reference manual

Basic ARM7tdmi block diagram

AMBA

0005A

PS2 keyboard PROTOCOL

80C552 i2c

AMBA APB UART

TSMC 0.18Um

80C552

AMBA peripheral

80C552

nvidia application notes

AMBA apb memory controller

AMBA APB bus protocol