AND8002 2012 B Search Results

MOTOROLA LOT MARKINGS

Abstract: On semiconductor date Code IC Lot Code Identification marking code 6L QFN tray qfn 4x4 AND8002 ase qfn unisem QFN marking code onsemi Diode on alpha year and work week
Contextual Info: AND8002/D Clock Generation and Clock and Data Marking and Ordering Information Guide http://onsemi.com Prepared by: Paul Shockman ON Semiconductor APPLICATION NOTE Introduction This application note describes the device markings and ordering information for the following ON Semiconductor

KPT22

Contextual Info: MC100EPT22 3.3V Dual LVTTL/LVCMOS to Differential LVPECL Translator Description The MC100EPT22 is a dual LVTTL/LVCMOS to differential LVPECL translator. Because LVPECL Positive ECL levels are used only +3.3 V and ground are required. The small outline 8−lead

MC100EPT21DG

Contextual Info: MC100EPT21 3.3V Differential LVPECL/LVDS/CML to LVTTL/LVCMOS Translator The MC100EPT21 is a Differential LVPECL/LVDS/CML to LVTTL/LVCMOS translator. Because LVPECL Positive ECL , LVDS, and positive CML input levels and LVTTL/LVCMOS output levels are used, only +3.3 V and ground are required. The small

488AM

Abstract: lqfp-32 footprint layout
Contextual Info: MC100LVEP210 2.5V / 3.3V 1:5 Dual Differential ECL/PECL/HSTL Clock Driver Description The MC100LVEP210 is a low skew 1−to−5 dual differential driver, designed with clock distribution in mind. The ECL/PECL input signals can be either differential or single−ended if the VBB output is

10H351

Contextual Info: MC10H351 Quad TTL/NMOS to PECL* Translator Description The MC10H351 is a quad translator for interfacing data between a saturated logic section and the PECL section of digital systems when only a +5.0 Vdc power supply is available. The MC10H351 has TTL/NMOS compatible inputs and PECL complementary

Contextual Info: MC100LVELT22 3.3V Dual LVTTL/LVCMOS to Differential LVPECL Translator Description Features • • • • • • • 350 ps Typical Propagation Delay <100 ps Output−to−Output Skew Flow Through Pinouts The 100 Series Contains Temperature Compensation

lqfp-32 footprint layout

Abstract: MC100LVEP111MNG MC100LVEP111 AN1568 MC100LVEP111FARG M100LVEP111FATW M100LVEP111FATWG MC100LVEP111MNRG MC100LVEP111FAG
Contextual Info: MC100LVEP111 2.5V / 3.3V 1:10 Differential ECL/PECL/HSTL Clock Driver Description The MC100LVEP111 is a low skew 1−to−10 differential driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The PECL input signals can be either differential or

KR22

Contextual Info: MC100LVELT22 3.3V Dual LVTTL/LVCMOS to Differential LVPECL Translator Description Features • • • • • • • 350 ps Typical Propagation Delay <100 ps Output−to−Output Skew Flow Through Pinouts The 100 Series Contains Temperature Compensation

MC100LVEP111

Contextual Info: MC100LVEP111 2.5V / 3.3V 1:10 Differential ECL/PECL/HSTL Clock Driver Description The MC100LVEP111 is a low skew 1−to−10 differential driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The PECL input signals can be either differential or

3n551

Abstract: 3n55 NB3N551DG
Contextual Info: NB3N551 3.3 V / 5.0 V Ultra-Low Skew 1:4 Clock Fanout Buffer Description The NB3N551 is a low skew 1−to 4 clock fanout buffer, designed for clock distribution in mind. The NB3N551 specifically guarantees low output−to−output skew. Optimal design, layout and processing

Contextual Info: NB3N106K 3.3V Differential 1:6 Fanout Clock Driver with HCSL Outputs Description The NB3N106K is a differential 1:6 Clock fanout buffer with High−speed Current Steering Logic HCSL outputs optimized for ultra low propagation delay variation. The NB3N106K is designed

Contextual Info: NB3L14S 2.5 V 1:4 LVDS Fanout Buffer The NB3L14S is a differential 1:4 LVDS Clock fanout buffer. The differential inputs incorporate internal 50 W termination resistors that are accessed through the VT pin. The NB3L14S LVDS signals will be buffered and replicated to identical LVDS copies of the Input

Contextual Info: NB3L553 2.5 V / 3.3 V / 5.0 V 1:4 Clock Fanout Buffer Description The NB3L553 is a low skew 1−to 4 clock fanout buffer, designed for clock distribution in mind. The NB3L553 specifically guarantees low output−to−output skew. Optimal design, layout and processing

Contextual Info: NB3L83948C 2.5 V / 3.3 V Differential and LVTTL/LVCMOS 2:1 MUX to 1:12 LVCMOS Fanout Description The NB3L83948C is a pure 2.5 / 3.3 V VDD = VDDO or mixed mode 3.3 V Core (VDD) / 2.5 V Output (VDDO) clock distribution buffer with the capability to select either a differential LVPECL /

QFN-16 agilent

Abstract: 120WW NB6L14MNG
Contextual Info: NB6L14 2.5 V/3.3 V 3.0 GHz Differential 1:4 LVPECL Fanout Buffer Multi−Level Inputs with Internal Termination http://onsemi.com Description MARKING DIAGRAM* The NB6L14 is a 3.0 GHz differential 1:4 LVPECL clock or data fanout buffer. The differential inputs incorporate internal 50 W

NB7L14MMNG

Contextual Info: NB7L14M 2.5V/3.3V Differential 1:4 Clock/Data Fanout Buffer/ Translator with CML Outputs and Internal Termination http://onsemi.com MARKING DIAGRAM* Description The NB7L14M is a differential 1−to−4 clock/data distribution chip with internal source terminated CML output structures, optimized for

Contextual Info: NB7L86M 2.5V/3.3V 12 Gb/s Differential Clock/Data SmartGate with CML Output and Internal Termination The NB7L86M is a multi−function differential Logic Gate, which can be configured as an AND/NAND, OR/NOR, XOR/XNOR, or 2:1 MUX. This device is part of the GigaComm family of high

footprint soic20

Contextual Info: MC10EP139, MC100EP139 3.3V / 5V ECL ÷2/4, ÷4/5/6 Clock Generation Chip Description The MC10/100EP139 is a low skew ÷2/4, ÷4/5/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common

Contextual Info: NB3H83905C 1.8V/2.5V/3.3V Crystal Input to 1:6 LVTTL/LVCMOS Clock Fanout Buffer with OE Description The NB3H83905C is a 1.8 V, 2.5 V or 3.3 V VDD core Crystal input to 1:6 LVTTL/LVCMOS fanout buffer with outputs powered by flexible 1.8 V, 2.5 V, or 3.3 V supply VDDO with VDD w VDDO . The

QFN tray 3x3

Abstract: qfn 3x3 tray dimension
Contextual Info: NBSG86A 2.5V/3.3V SiGe Differential Smart Gate with Output Level Select The NBSG86A is a multi−function differential Logic Gate which can be configured as an AND/NAND, OR/NOR, XOR/XNOR, or 2:1 MUX. This device is part of the GigaComm family of high

5621 transistor

Abstract: 4gd1
Contextual Info: NB6L295 2.5V / 3.3V Dual Channel Programmable Clock/Data Delay with Differential LVPECL Outputs Multi−Level Inputs w/ Internal Termination The NB6L295 is a Dual Channel Programmable Delay Chip http://onsemi.com designed primarily for Clock or Data de−skewing and timing

NB6L295MMN

Contextual Info: NB6L295M 2.5V / 3.3V Dual Channel Programmable Clock/Data Delay with Differential CML Outputs Multi−Level Inputs w/ Internal Termination The NB6L295M is a Dual Channel Programmable Delay Chip http://onsemi.com designed primarily for Clock or Data de−skewing and timing