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    ANTIFUSE FPGA Search Results

    ANTIFUSE FPGA Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    TE512S32-25LC Rochester Electronics LLC TE512S32 - Field Programmable Gate Array, CMOS, PQFP128 Visit Rochester Electronics LLC Buy
    TE505S16-40QC-G Rochester Electronics LLC TE505S16 - Field Programmable Gate Array, CMOS, PQFP208 Visit Rochester Electronics LLC Buy
    TE505S16-40QI Rochester Electronics LLC TE505S16 - Field Programmable Gate Array, CMOS, PQFP208 Visit Rochester Electronics LLC Buy
    TE505S16-25QC-G Rochester Electronics LLC TE512S32 - Field Programmable Gate Array, CMOS Visit Rochester Electronics LLC Buy
    TE512S32-40LC Rochester Electronics LLC TE512S32 - Field Programmable Gate Array, CMOS, PQFP128 Visit Rochester Electronics LLC Buy

    ANTIFUSE FPGA Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    antifuse

    Abstract: actel act1 family ANTIFUSE-based actel antifuse programming technology
    Text: Back Actel and the Antifuse Page 1 of 5 Actel and the Antifuse • • • • • • • • Introduction Antifuse vs Memory-based Programmable Logic Antifuse Technology Evaluating Antifuse Alternatives User Benefits of Actel's PLICE Technology Future Directions in Antifuse Technology


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    vhdl code for motor speed control

    Abstract: ANTIFUSE
    Text: Actel’s Antifuse FPGAs Programmable ASIC Solutions Space Electronics Communications Infrastructure e-Appliances The Antifuse Advantage Actel’s antifuse devices are low-cost, high-performance solutions for today’s logic designer. Ideal for integrating logic typically implemented in multiple CPLDs, PALs,


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    fpga JTAG Programmer Schematics

    Abstract: antifuse programming technology ANTIFUSE
    Text: Actel’s Antifuse FPGAs Single Chip High Performance Solutions S e i x i n g N o O M P R c e F u r n P i The Antifuse Advantage Save Some Money With a smaller switching element and a smaller die size, Actel’s antifuse FPGAs provide a substantial cost advantage over equivalent SRAM


    Original     		PDF 64-bit 32-bit 64-bit fpga JTAG Programmer Schematics antifuse programming technology ANTIFUSE

    Actel a1280

    Abstract: BP-1710 ACTEL A1010 rt1280 ACTEL A1010A Silicon Sculptor II bp1710 RT54SX72SU Actel A1020 Actel a1225xl
    Text: Application Note AC225 Programming Antifuse Devices Introduction This document provides an overview of the various programming options available for the Actel antifuse families. In addition, it provides helpful information relating to programming failures, including measures


    Original     		PDF AC225 Actel a1280 BP-1710 ACTEL A1010 rt1280 ACTEL A1010A Silicon Sculptor II bp1710 RT54SX72SU Actel A1020 Actel a1225xl

    RT54SX72SU

    Abstract: rt54sx32su silicon sculptor 3 54SX16A BP-1710 rt1280 Actel a1280 ACT2 A1280 AC225 A32140DX PQ208
    Text: Application Note AC225 Programming Antifuse Devices Introduction This document provides an overview of the various programming options available for the Actel antifuse families. In addition, it provides helpful information relating to programming failures, including measures


    Original     		PDF AC225 RT54SX72SU rt54sx32su silicon sculptor 3 54SX16A BP-1710 rt1280 Actel a1280 ACT2 A1280 AC225 A32140DX PQ208

    Dielectric Constant Silicon Nitride

    Abstract: Amorphous AS antifuse pp186 pp151-153
    Text: RELIABILITY MECHANISM OF THE UNPROGRAMMED AMORPHOUS SILICON ANTIFUSE by Richard J. Wong and Kathryn E. Gordon 7 7-15 Reprints Presented at the International Reliability and Physics Symposium April 1994 Copyright IEEE 1994 IRPS 1994 REPRINT Abstract Amorphous Silicon Antifuse Structure


    Original     		PDF pp292-294. QL8x12 QL12x16 QL16x24 QL24x32 400nA 200nA 100nA 140nA 82MV/cm Dielectric Constant Silicon Nitride Amorphous AS antifuse pp186 pp151-153

    how to make ic copier

    Abstract: schematic 80386 ANTIFUSE
    Text: Design Security in Nonvolatile Flash and Antifuse FPGAs White Paper 2001 Actel Corporation All Rights Reserved. Actel and the Actel logo are trademarks of Actel Corporation. All other brand or product names are the property of their respective owners. 2


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    cpu Intel 4040

    Abstract: intel 4040 3com 226 QAN19 Modulating Direct Digital Synthesizer in a QuickLogic FPGA QL3025 pASIC 1 Family 4040 cmos 4040 intel cmos 4040 datasheet
    Text: LEADING THE REVOLUTION IN FPGAs The Vialink Antifuse in 0.35µm CMOS QuickLogic Corporation 1277 Orleans Dr. Sunnyvale, CA 94089-1138 General Information: Applications Hotline FAX: EMAIL: WEB SITE: 408 990-4000 (408) 990-4100 (408) 990-4040 info@quicklogic.com


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    Actel on sram

    Abstract: AC140
    Text: Application Note AC140 Design for Low Power in Actel Antifuse FPGAs As system power budgets grow tighter, the need for lower power components becomes more critical. For communications infrastructure applications, board cooling, cabinet space minimization, and system reliability all play a


    Original     		PDF AC140 Actel on sram AC140

    CPGA routing

    Abstract: No abstract text available
    Text: pASIC 1 Family ViaLink Technology Very-High-Speed CMOS FPGAs FAMILY HIGHLIGHTS Very High Speed – ViaLink metal-to-metal, programmable-via antifuse technology ensures useful internal logic function speeds at over 100 MHz, and logic cell delays of under 2 ns.


    Original     		PDF 14-input QL8x12B MIL-STD-883D, CPGA routing

    42MX36

    Abstract: A42MX16 Actel a42mx16 a42mx A42MX24 AC291 A42MX36 42MX ns845 Actel a42mx16 AC291
    Text: Application Note AC291 42MX Family Devices Power-Up Behavior Introduction Actel antifuse FPGA families offer the advantage of nonvolatility by attaining immediate functionality at power-up. Since the programmed design is retained, there is no requirement for additional configuration


    Original     		PDF AC291 42MX36 A42MX16 Actel a42mx16 a42mx A42MX24 AC291 A42MX36 42MX ns845 Actel a42mx16 AC291

    vhdl code for watchdog timer of ATM

    Abstract: zilog 3570 z80 vhdl vhdl code for a 16*2 lcd vhdl code for rs232 receiver vhdl code for ethernet csma cd VHDL rs232 driver 1553b VHDL A24D16 vme vhdl
    Text: IP Solutions Improve Time-to-Market and Reduce Design Risk Actel’s IP Solutions — Complement Actel’s Nonvolatile, Secure, Low-Power Antifuse and Flash FPGAs — Available in Evaluation, RTL, and Netlist Formats — Offer Single- and Multiple-Use Licenses


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    RTAX1000S-SL

    Abstract: RTAX2000 actel PLL schematic LVCMOS25 signal path designer JESD8-11
    Text: Application Note AC310 RTAX-S/SL Clocking Resource and Implementation Introduction Actel's RTAX-S/SL FPGA family offers the most flexible global network scheme of any antifuse-based FPGA to date. This architecture provides eight segmentable chip-wide global networks, and dedicated power-on


    Original     		PDF AC310 RTAX1000S-SL RTAX2000 actel PLL schematic LVCMOS25 signal path designer JESD8-11

    RT54SX32S-CQ208B

    Abstract: RT54SX72SCQ208 RT1280A-CQ172 Actel A1020B RT54SX16S-CQ256B 30-80LET Single Event Latchup FPGA
    Text: Actel FPGAs for Space Applications Uncompromising in the Extreme n n n n n Total Dose Capabilities from 5Krads to 1M rad Latch-up Immune Device Capacities from 4,000 to 72,000 Available Gates Highly Reliable, Non-Volatile Antifuse Technology Meets the Most Stringent Quality


    Original     		PDF 1-888-99-ACTEL RT54SX32S-CQ208B RT54SX72SCQ208 RT1280A-CQ172 Actel A1020B RT54SX16S-CQ256B 30-80LET Single Event Latchup FPGA

    CG624

    Abstract: SK-AX1-AX2-KITTOP AX1000-CG624 RTAX2000 RTAX1000SL-CG624 CCGA AX2000-CG624 FG484 SK-AX2-CG624-KITBTM RTAX2000S
    Text: Application Note AC275 CCGA to FBGA Adapter Sockets Introduction Actel recently introduced RTAX-S/L, the next generation designed-for-space antifuse Field Programmable Gate Arrays FPGAs . RTAX-S/L, with up to four million system gates, is Actel's highest density family,


    Original     		PDF AC275 CG624 SK-AX1-AX2-KITTOP AX1000-CG624 RTAX2000 RTAX1000SL-CG624 CCGA AX2000-CG624 FG484 SK-AX2-CG624-KITBTM RTAX2000S

    ttl logic gates

    Abstract: pASIC 1 Family ttl and gate
    Text: pASIC 1 Family ViaLink Technology Very-High-Speed CMOS FPGAs FAMILY HIGHLIGHTS Very High Speed – ViaLink metal-to-metal, programmable-via antifuse technology ensures useful internal logic function speeds at over 100 MHz, and logic cell delays of under 2 ns.


    Original     		PDF 14-input MIL-STD-883D, ttl logic gates pASIC 1 Family ttl and gate

    antifuse programming technology

    Abstract: antifuse XC8100 XC9500
    Text: Mike Seither Xilinx, Inc. 408 879-6557 mike.seither@xilinx.com FOR IMMEDIATE RELEASE XILINX DISCONTINUES ANTIFUSE PRODUCT DEVELOPMENT Mainstream SRAM- and FLASH-based technologies to serve market SAN JOSE, Calif., July 31, 1996—Citing the strong market acceptance of SRAM


    Original     		PDF 1996--Citing XC8100 antifuse programming technology antifuse XC9500

    RTSX32

    Abstract: RT54SX72S AC308 A42MX16 A54SX32A A54SX72A MX16 RTSX72-S Signal Path Designer
    Text: Application Note AC308 Metastability Characterization Report for Actel Antifuse FPGAs Introduction Whenever asynchronous data is registered by a clocked flip-flop, there is a probability of setup or hold time violation on that flip-flop. In applications such as synchronization or data recovery, due to the


    Original     		PDF AC308 RTSX32 RT54SX72S AC308 A42MX16 A54SX32A A54SX72A MX16 RTSX72-S Signal Path Designer

    42MX36

    Abstract: 42MX24 42MX16 ns845
    Text: Application Note 42MX Family Devices Power-Up Behavior I n tro du ct i on Actel antifuse FPGA families offer the advantage of nonvolatility by attaining immediate functionality at power up. Since the programmed design is retained, there is no requirement for additional configuration devices. This


    Original     		PDF

    Untitled

    Abstract: No abstract text available
    Text: QL8x12BL pASIC 1 Family Low Power 3.3 Volt Operation FPGA pASIC HIGHLIGHTS High Speed - ViaLink" metal-to-metal programmable-via antifuse technology, allows counter speeds over 80 MHz at 3.3 Volt operation. 5Y Tolerant I/Os - Support interface to 5 Volt CMOS, NMOS and


    OCR Scan     		PDF QL8x12BL 8-by-12 44-pin 68-pin 100-pin 8x12BL PL68C 68-pin PF100

    Untitled

    Abstract: No abstract text available
    Text: QL12x16BL pASIC 1 Family Low Power 3.3 Volt Operation FPGA pASIC HIGHLIGHTS High Speed - ViaLink" metal-to-metal programmable-via antifuse technology, allows counter speeds over 80 MHz at 3.3 Volt operation. 5Y Tolerant I/Os - Support interface to 5 Volt CMOS, NMOS and


    OCR Scan     		PDF QL12x16BL 12-by-16 68-pin 84-pin 100-pin QL12xl6B 12x16BL PF100

    Untitled

    Abstract: No abstract text available
    Text: QL16x24BL pASIC 1 Family Low Power 3.3 Volt Operation FPGA pASIC HIGHLIGHTS High Speed - ViaLink" metal-to-metal programmable-via antifuse technology, allows counter speeds over 80 MHz at 3.3 Volt operation. 5Y Tolerant I/Os - Support interface to 5 Volt CMOS, NMOS and


    OCR Scan     		PDF QL16x24BL 16-by-24 84-pin 100-pin 144-pin QL16x24B QL16X2VO 16X24BL F144C 84-pin

    quicklogic pasic

    Abstract: No abstract text available
    Text: WS * 3 1391 pASIC 1 FAMILY V iaLink™ Technology V ery H igh Speed CMOS FPGAs PRELIMINARY DATA FAMILY HIGHLIGHTS B May 1991 Very High Speed - ViaLink™ Metal-to-metal programmable-via antifuse technology, ensures counter speeds over 100 MHz, and logic


    OCR Scan     		PDF 16-bit quicklogic pasic

    ttl and gate

    Abstract: No abstract text available
    Text: pASIC 1 Family ViaLink Technology Very-High-Speed CMOS FPGAs FAMILY HIGHLIGHTS Q Very High Speed - ViaLink metal-to-metal, programmable-via antifuse technology ensures useful internal logic function speeds at over 100 MHz, and logic cell delays of under 2 ns.


    OCR Scan     		PDF 14-input MIL-STD-883D, ttl and gate