ASIC 100K GATES Search Results

CX2001

Abstract: CX2121 "CHIP EXPRESS" CHIPX CX2041 CX2081 CX2201
Contextual Info: CX2001 0.6µ µm CMOS Fast-Turn ASIC Product Introduction The CX2001 is a fast-turn, 0.6µm CMOS triple-metal module array product. The CX2001 features density ranges from 23k to 100k usable gates, up to 96k bits of configurable embedded RAM / ROM, and up

Chip Express

Abstract: CHIPX CX2001 CX2041 CX2081 CX2121 CX2201 "Single-Port RAM" "CHIP EXPRESS"
Contextual Info: CX2001 0.6µ µm CMOS Fast-Turn ASIC Product Family Introduction The CX2001 is a fast-turn, 0.6µm CMOS triple-metal module array product. The CX2001 features density ranges from 23k to 100k usable gates, up to 96k bits of configurable embedded RAM / ROM, and up

str 6307

Abstract: str 6307 datasheet STR 6307 POWER ic str 6307 D-71229 STR S 6307
Contextual Info: Low Power CMOS ASIC 0.3µm 3V/2V TC222C Series Cell-Based IC PRODUCT GUIDE Overview features help to substantially reduce your chip’s power while maximizing the critical path speed. Power Comparison e.g., 100k gates, 70k-bit SRAM, 20MHz Core : 3V Core : 2V, I/Os : Single 3V

str 6307 datasheet

Abstract: str 6307 D-71229 ic str 6307 STR 6307 POWER STR S 6307 TC222C Toshiba Europe NAND
Contextual Info: Low Power CMOS ASIC 0.3µm 3V/2V TC222C Series Cell-Based IC PRODUCT GUIDE Overview features help to substantially reduce your chip’s power while maximizing the critical path speed. Power Comparison e.g., 100k gates, 70k-bit SRAM, 20MHz Core : 3V Core : 2V, I/Os : Single 3V

Contextual Info: Quantum38K ISR™ CPLD Family PRELIMINARY CPLDs at ASIC Prices™ Features • High density — 30K to 100K usable gates — 512 to 1536 macrocells — 136 to 302 maximum I/O pins — 8 Dedicated Inputs including 4 clock pins and 4 global I/O control signal pins; 4 JTAG interface pins

WIDE BUS FAMILY

Contextual Info: Quantum38K ISR™ CPLD Family PRELIMINARY CPLDs at ASIC Prices™ Features • High density — 15K to 100K usable gates — 256 to 1536 macrocells — 92 to 302 maximum I/O pins — 8 Dedicated Inputs including 4 clock pins and 4 global control signal pins; 4 JTAG interface pins for

CY3LV010

Abstract: 38K30 CYDH2200E 38K50
Contextual Info: Quantum38K ISR™ CPLD Family PRELIMINARY CPLDs at ASIC Prices™ Features • High density — 30K to 100K usable gates — 512 to 1536 macrocells — 136 to 302 maximum I/O pins — Eight Dedicated Inputs including four clock pins and four global I/O control signal pins; four JTAG interface pins for reconfigurability/boundary scan

Contextual Info: Perspective Year 2000 Worldwide Xilinx Event Schedules Design Reuse Moore’s Law Gates / designer / day Engineering Productivity Year 2000 North American Event Schedule Sept 6-7 Embedded Internet Conference 2000 San Jose, CA Sept 20 SNUG 2000 Boston Boston, MA

"CHIP EXPRESS"

Abstract: CX2000 CX2201 CX2041 CX2081 CX2121 CHIP EXPRESS
Contextual Info: CX2000 0.6um Advanced Gate Array 1. Product Description The CX2000, 0.6um Advanced Gate Array product family features density ranges from 23K to 100K usable gates, up to 96K bits of configurable embedded RAM / ROM, and up to 556 I/Os. Using Chip Express’ proprietary architecture, fast-turn delivery of prototypes and production is achieved. Seamless

PC5023

Abstract: asic 100k gates mpc5023
Contextual Info: Road map Semi-Custom IC Semi-Custom IC Cell-Based IC What is the most suitable ASIC product for you? Road map Line-Up Comparison of performance of each series Gate Array Transition of power consumption Road map What is the most suitable Gate Array for you?

SPARTAN-II xc2s100 pq208

Abstract: XC2S100 SPARTAN XC2S50 SPARTAN-II xc2s50 pq208 XC2S50 xc2s30 tq144 XC2S150 PQ208 SPARTAN 6 peripherals datasheet XC2S30 board xc2s30 pq208
Contextual Info: Xilinx Confidential and Restricted Page 1 January 6, 2000 Agenda • Spartan Philosophy • Spartan-II FPGAs: Extending Spartan Series • System Integration • Spartan-II family: ASSP Replacement • Summary Xilinx Confidential and Restricted Page 2 January 6, 2000

720-Progressive

Abstract: Reed-Solomon CODEC XCS20XL-4TQ144 Reed Solomon decoder IC SPARTAN 6 ethernet datasheet DS80C320 480-Line lsi Reed-Solomon CODEC Xilinx Spartan-II 2.5V FPGA Family internal structure
Contextual Info: White Paper: Spartan-II The Spartan-II Family – The Complete Package R WP106 v1.0 January 10, 2000 Introduction Author: Krishna Rangasayee The Spartan -II Family, Combined with a Vast Soft IP Portfolio is the First Programmable Logic Solution to Effectively Penetrate the ASSP

XAPP120

Abstract: XCS05 XCS05XL XCS10 XCS10XL XCS20 XCS20XL rm901
Contextual Info: APPLICATION NOTE  XAPP120 December 2, 1998 Version 1.1 How Spartan Series FPGAs Compete for Gate Array Production Application Note by Ashok Chotai Summary This application note discusses the enormous progress made by FPGAs in the areas of technology, low-price and

SPARTAN-II xc2s50 pq208

Abstract: XC2S100 SPARTAN-II xc2s100 pq208 SPARTAN-II XC2S50 XC2S30 board
Contextual Info: Cover Story THE NEW Spartan-I I FPGA Family KISS YOUR AS IC GOOD-BYE Spartan FPGAs are experiencing tremendous growth due to their inherent advantages over ASICs. Device System Gates Logic Cells Block RAM Bits Block RAM Blocks he Spartan Series FPGAs, introduced by

fpga spartan 2

Contextual Info: FPGAs vs. ASICs FPGAs Can Be an by Steve Sharp, sharp@xilinx.com Effective Alternative to Mask Gate Arrays In this fast-paced electronics industry, gate array engineers are under increasing pressure to produce new ASIC designs ever more quickly. As traditional masked gate arrays decline in usage, a

Contextual Info: M0T0#70Z.>1 Semiconductor ASIC Division PRODUCT PREVIEW MOTOROLA MCA50000ECL and MCA50000CDA ARRAYS Motorola's MCA50000 Array family is a family of ECL arrays designed with Motorola's MOSAIC-4 1.0u trench Process Technology. The arrays are designed primarily to meet the

quickturn realizer

Abstract: Roberta Fulton XC4000XV
Contextual Info: by Roberta Fulton, Alliance EDA Technical Marketing Engineer, roberta@xilinx.com 24 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○

SPARTAN-II xc2s50 pq208

Abstract: SPARTAN-II xc2s100 pq208 SPARTAN XC2S50 XC2S100 XC2S50 SPARTAN Xilinx SPARTAN CS144 FG256 PQ208
Contextual Info: Cover Story THE NEW Spartan-I I FPGA Family KISS YOUR AS IC GOOD-BYE Spartan FPGAs are experiencing tremendous growth due to their inherent advantages over ASICs. Device System Gates Logic Cells Block RAM Bits by Jay Aggarwal, Product Marketing Manager , Spartan Series, Xilinx, jay.aggarwal@xilinx.com

a1698

Abstract: 8B10B asic nec 928 Cell-based ASIC 8B10B
Contextual Info: ISSP/150 nm ASIC Technology ISSP1 - High-Speed Interface Family Product Letter Description The ISSP1-HSI, the Instant Silicon Solutions PlatformTM ISSP High-Speed Interface (HSI) family, is a new class of ASIC device that features built-in, highspeed Serializer/Deserializer (SerDes) transceiver cores. Ideal for mid-volume

Contextual Info: DATA SHEET VITESSE FX-M Family High Performance Gate Arrays for Military Applications SEMICONDUCTOR CORPORATION Features • Superior Perform ance: High Speed and Low Pow er Dissipation 5 Arrays from 20K to 35 0 K Gates • Mature, Rad iation Hard, G aA s E nhancem ent/

BR931

Abstract: motorola mca MCA3200ETL MCA6200ETL MCA750ETL H4C018 Motorola Master Selection Guide H4C161 wirebond die flag lead frame an1512
Contextual Info: Semicustom Application Specific Integrated Circuits In Brief . . . Motorola supports strategic programs and co–development partnerships to accelerate the availability of advanced processes CMOS, BiCMOS, Bipolar , packaging and CAD technology. Extensive research,

the application of fpga in today

Abstract: Exemplar Logic XCV50
Contextual Info: FOR IMMEDIATE RELEASE Exemplar Logic announces support for Xilinx Virtex Series FPGAs Fremont, California – October 26, 1998 – Exemplar Logic, the world leader in FPGA synthesis today announced the immediate support for Xilinx Virtex Series FPGAs in LeonardoSpectrum.

CX3002

Abstract: "CHIP EXPRESS" 2308 rom CHIPX CHIP EXPRESS
Contextual Info: CX3002 0.35um CMOS ASIC Production Family available that permit options for rapid turnaround time and scalable volume production. The CX3002 product services those applications requiring ASIC performance in the networking, communications, computing, and industrial marketplace.

SH100E

Abstract: siemens SH100E elxr siemens Nand gate SH100E5 TRANSISTOR K 2191
Contextual Info: 7 1991 SIEMENS ASIC Product Description SH100E ECL/CML Gale Amy Family FEATURES • Gate complexities from 1,500 to 16,000 gates ■ 120 ps gate delay, 90 ps differential • 1.5 GHz D flip-flop, 1.7 GHz differential ■ Both ECL and CML macro families ■ TTL I/O available