B1 9A Search Results

Fairchild 9614

Abstract: ttl 7440 TTL 7437 15 1E78 la733 74H40 RS232 TTL 8T13 8T14 8T23
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS INTERFACE 12 9614 II MA733 G2A ACTIVE PULL UP A1 GTA GAIN SELECT ACTIVE PULL UP B2 ACTIVE PULL UP A2 OUT B1 ACTIVE PULL UP B1 IN A3 3 IN B1 Flatpàk and Dip Not Shown 14 9616 13 9615 INA1 |14 H VCC+ 13 ^ IN B1 \2 T IN A2

Contextual Info: EAA*7BCAA* ;B0/;@>?5/0!;5>1 #;B1=0&@<<8D ,<DB18897805669395>3I0C,0C9J5 BF F # 030#,0#"*% :1C?031:1=-?5;:0<;B1=0>;8@?5;: '(%&030"#'"!&0 ' -:

Contextual Info: EAA*7AA* 8?=-0;B0!;5>10 #;B1=0&@<<8D ,<DB18897805669395>3I0C,0C9J5 48D98E #(030#,0#"*% :1C?031:1=-?5;:0<;B1=0>;8@?5;: '(%&030"#'"!&0 '410 +0 2-958D0 ;20 (8?=-0 ;B0 !;5>10 <;B1=0 >@<<851>0 <=;A501>0 @<0 ?;0 AA*0 5:0 -:

Contextual Info: CAA*7EAA* 8?=-0;B0!;5>10 #;B1=0&@<<8D ,<DB18897805669395>3I0C,0C9J5 48D98E #(030#,0#"*% :1C?031:1=-?5;:0<;B1=0>;8@?5;: '(%&030"#'"!&0 '410 +'0 2-958D0 ;20 (8?=-0 ;B0 !;5>10 <;B1=0 >@<<851>0 <=;A501>0 @<0 ?;0 EAA*0 5:0 -: 1C?=1918D0 /;9<-/?0 B(0 C0 CA990 C0 990 <-/7-3180 *5?40 1225/51:/51>0 ;20 @<0 ?;

SN76502

Abstract: SN56502 SN72741 SN7510 SN52741 SN72733 SN52741/SN76502 Logarithmic Amplifiers sn727*3 Logarithmic Amplifier detector
Contextual Info: COMMUNICATIONS CIRCUITS CIRCUIT TYPES SN56502, SN76502 LOGARITHMIC AMPLIFIERS JOR N D U A L - IN - L IN E P A C K A G E S T O P V IE W NC CB2 Cß2' GND IN PU T B1 16 15 14 13 12 10 Excellent Dynamic Range log B1 Wide Bandwidth n Built-In Temperature Compensation

1513GB172-3DW

Contextual Info: SKS B1 090 GD 69/11 - MA PB Absolute maximum ratings 1 Symbol IOUT MAX IIN MAX Conditions Maximum permanent output current Maximum permanent input current VOUT MAX VBUS MAX FOUT MAX FSW MAX Maximum output voltage Maximum DC Bus voltage Inverter output frequency

LM333T

Abstract: LM133KSTEEL LM333 B1238 b1225 K02A LM133 LM133K LM150 w190c
Contextual Info: LM133 LM333 3-Ampere Adjustable Negative Regulators General Description Features The LM133 LM333 are adjustable 3-terminal negative voltage regulators capable of supplying in excess of b3 0A over an output voltage range of b1 2V to b32V These regulators are exceptionally easy to apply requiring only 2

Contextual Info: PI5C32161C 16-Bit to 32-Bit, DeMux PCI Hot-Plug Bus Switch with –2V Undershoot Protection Features Description • • • • • • • • • • RON is 5Ω typical Precharge on B1 and B2 ports minimizes line insertion noise Undershoot protection on A port only: –2V

CT502

Abstract: 23B4 RA523-3 B706 CB546 13b3 22b3 VGA3M B403 CB-501
Contextual Info: 5 Schematic Diagrams and PCB Silkscreen 5-1-2 Signal Location Signal Name Sheet Number - Location Signal Name Sheet Number - Location AD_SEL 16-B2, 17-B4, 23-B1, 26-D3 CBA3_CCBE3* 9-D3, 10-B4, 25-A2 ADAPTOR_IN 17-B3, 26-C3 CBA3_CCD1* 9-C4, 10-C1, 10-D4, 25-B2

Contextual Info: 'to .tra m e .b rev. B1 2000/08/01 74651 10 -*1* -*3* £• ¡\ to 1" -*7* -*4* £■ f 9aH 1m * © © DAUGHTERCARD CONNECTOR SIDE PAR T NUMBER 74651-25*1 74651-25*6 74651-10*2 74651-10*7 74651-25*2 74651-25*7 74651-10*3 74651-10*8 74651-25*3 74651-25*8

BURNER

Contextual Info: 4 3 THIS DRAWING IS UNPUBLISHED. COPYRIGHT RELEASED FOR PUBLICATION BY TYCO ELECTRONICS CORPORATION. - 2 — , ALL RIGHTS RESERVED. LOC DIST AF 50 R EVIS IO N S LTR DESCRIPTION B1 4.32 [.1 70] D REVISED PER E C R - 0 5 - 0 0 5 7 1 6 1 CONTINUOUS STRIP ON

2096E

Contextual Info: ispLSI 2096E In-System Programmable SuperFAST High Density PLD Features Functional Block Diagram Output Routing Pool ORP D3 D4 D2 D1 D0 A0 C7 A1 C6 A4 Q D Q C5 C4 Y A3 D Logic Array R A5 A6 D Q D Q C3 GLB C2 C1 Global Routing Pool (GRP) A A7 B0 B1

Contextual Info: Package Outlines Plastic Packages MO-093AA E A ØP 5 LEAD JEDEC MO-093AA PLASTIC PACKAGE A1 INCHES Q H1 TERM. 6 D L1 b1 L c 75o 1 2 3 4 5 b e J1 e1 MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A 0.185 0.195 4.70 4.95 - A1 0.058 0.062 1.48 1.57 - b 0.049 0.053

Contextual Info: TMS370Cx6x 8-BIT MICROCONTROLLER SPNS033C – SEPTEMBER 1995 – REVISED FEBRUARY 1997 D D D D D D FN / FZ PACKAGE TOP VIEW VSS1 C2 C1 MC C0 B7 B6 B5 B4 B3 B2 B1 B0 T2BIC1/CR VCC2 VSS2 VCC1 CMOS/EEPROM/EPROM Technologies on a Single Device – Mask-ROM Devices for High-Volume

mark AT0

Abstract: 676-Pin B27 QFN ACTEL FBGA 144 R13NC IO30PDB1V1 IO06PDB0V1 IO10PDB0V1 AFS090
Contextual Info: Actel Fusion Mixed-Signal FPGAs 4 – Package Pin Assignments 108-Pin QFN A44 A56 B41 B52 Pin A1 Mark A1 A43 B40 B1 B13 A14 B27 A29 B26 B14 A28 A15 Note: The die attach paddle center of the package is tied to ground GND . Note For Package Manufacturing and Environmental information, visit the Resource Center at

SE370C758B

Abstract: SE370C756A TMS370C756A
Contextual Info: TMS370Cx5x 8-BIT MICROCONTROLLER SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997 D D D D D D D D D FN / FZ PACKAGE TOP VIEW VSS1 C2 C1 MC C0 B7 B6 B5 B4 B3 B2 B1 B0 D0 / CSE2 / OCF VCC2 VSS2 VCC1 CMOS/EEPROM/EPROM Technologies on a Single Device – Mask-ROM Devices for High-Volume

9624

Abstract: 11C24 11C44 11C58 E106 10125 ecl to ttl
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS INTERFACE I8 9622 17 9621 19 9624 GND [ I 2 Nc Q 3 IN A l C 4 IN A 2 ^ 5 IN A3 Q 6 IN A O Q 7 Vd d L f t •14 □ vcc 13 □ tap 12 □ nc 11 □ in B3 10 J in B2 9 □ in B1 8 □ OUT B 112 9650 110 111 9625 9627 1 GND

surface mount transistor A55

Abstract: surface mount transistor A48 c60 equivalent CR0805 irf150 rd sot23 sn74ls574 sot223, 31 64 sot23 a36 AD30
Contextual Info: P3V VIO P2 P1 NDA # VDD_PCI A1 1 P3V VIO VIO 1 B1 VDD_PCI A2 2 +12V_PCI A3 3 TCK A4 4 2 B2 TOOL1 3 B3 TMS X8 TDI X9 1 TDO 1 1 4 B4 A6 6 X7 A8 8 A9 9 X11 A10 10 1 X12 1 X10 7 B7 1 X50 12 B12 A13 13 13 B13 A14 14 14 B14 GNT# 18 B18 REQ# A19 19 19 B19 AD30 AD26

Fairchild 9614

Abstract: 15 1E78 312-3 m 9625 TTL 7440 8T13 8T14 8T23 8T24 654S
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS INTERFACE 17 9621 I8 9622 19 9624 GND [ I 2 Nc Q 3 IN A l C 4 IN A 2 ^ 5 IN A3 Q 6 IN A O Q 7 Vd d L 111 110 9627 9625 f t •14 □ vcc 13 □ tap 12 □ nc 11 □ in B3 10 J in B2 9 □ in B1 8 □ OUT B 112 9650 1 GND

Voltage-to-Frequency Interface

Abstract: B1 9A 9650 1306B m 9625 DAC-08 TTL CMOS wj 6n
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS INTERFACE I8 9622 17 9621 19 9624 GND [ I 2 Nc Q 3 IN A l C 4 IN A 2 ^ 5 IN A3 Q 6 IN A O Q 7 Vd d L f t •14 □ vcc 13 □ tap 12 □ nc 11 □ in B3 10 J in B2 9 □ in B1 8 □ OUT B 112 9650 110 111 9625 9627 1 GND

74LS240

Abstract: 75108 74LS244 74S140 74LS241 74LS540 74LS541 E105
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS INTERFACE I8 9622 17 9621 19 9624 GND [ I 2 Nc Q 3 IN A l C 4 IN A 2 ^ 5 IN A3 Q 6 IN A O Q 7 Vd d L f t •14 □ vcc 13 □ tap 12 □ nc 11 □ in B3 10 J in B2 9 □ in B1 8 □ OUT B 112 9650 110 111 9625 9627 1 GND

Contextual Info: Jf^S $ "  ฀ a  ฀$;B1='=-:>5>?;= $=;0@/?฀&@99-=D 6MI[\YMZ 9I R฀')- .฀8AC฀),;@9฀3@6฀/@;@E7CCFBE;4>7฀*AH7C฀-FBB>J฀ + L ' -A@?3I฀ (&1- [ $9 )0( 6 )# R฀+F3>;8;76฀355AC6;@9฀EA฀$ ฀8AC฀E3C97E฀3BB>;53E;A@D

surface mount transistor A48

Abstract: CR0805 diode b26 8q diode sot23 AD11 AD30 MAGIC R30
Contextual Info: P3V VIO P2 P1 NDA # VDD_PCI A1 1 P3V VIO VIO 1 B1 VDD_PCI A2 2 +12V_PCI A3 3 TCK A4 4 2 B2 TOOL1 3 B3 TMS X8 TDI X9 1 TDO 1 1 4 B4 A6 6 X7 A8 8 A9 9 X11 A10 10 C20 10 16V 2 7227 6 B6 INTA# A7 7 1 X12 1 X10 7 B7 1 X50 1 1 C19 5 B5 A5 5 1 C54 10 16V 2 7227 C53

Contextual Info: %* ! %฀ B<  ฀#;B1=&=-:>5>?;= #=;0@/?฀%@99-=D 6MI[\YMZ R฀#562=฀7@C฀9:89฀7C6BF6?4J฀DH:E49:?8฀2?5฀DJ?4 ฀C64 R฀ AE:>:K65฀E649?@=@8J฀7@C฀ ฀4@?G6CE6CD R฀I46=6?E฀82E6฀492C86฀I฀' 9I"\[#฀AC@5F4E฀ )'