BM DM HE NU Search Results

WTL 2265-060

Contextual Info: WTL 2264/WTL 2265 FLOATING POINT MULTIPLIER/ DIVIDER AND ALU PRELIMINARY DATA July 1986 Features HIGH SPEED FULL INTERNAL 64-BIT ACCUM ULATION PATH WTL 2265 20 MFlops (50 ns) pipelined for 32-bit ALU opera­ tions and 64-bit accumulations 20 M Flops (50 ns) pipelined for 32-bit multiplications

L3AP

Abstract: CL 2183 ic DSP-2183
Contextual Info: ANALOG DEVICES DSP Microcomputer ADSP-2183 FUNCTIONAL BLOCK DIAGRAM FEATURES PERFORMANCE 25 ns Instruction Cycle Tim e from 20.00 M Hz Crystal @ 3.3 Volts 33 MIPS Sustained Performance Single-Cycle Instruction Execution Single-Cycle C ontext Switch 3-Bus Architecture Allow s Dual Operand Fetches in

TC35860

Contextual Info: 622M bps ATM Segmentation and Reassembly Chipset 1 9 9 8 TC35860F TC35861F REVISION D A T A 1 . 0 B B O O K 00_legal 2/14/97 8:26 AM Page 1 1997 To shib a A m e rica E le c tro n ic C o m p o n e n ts, Inc. P u b lishe d in Ja nu ary, 1997 Toshiba products described in this document are not authorized for use as critical components in life support systems without the written consent of the appropriate officer of Toshiba

wtec III

Abstract: 001H LC7233N RE32 41176
Contextual Info: Ordering number: EN Í& 4 Í1 7 _ N o .*4117 SAXYO i CMOSLSI _ LC7233N Single-chip PLL and Microcontroller with LCD Driver Preliminary OVERVIEW PINOUT The LC7233N is a single-chip microcontroller that incorporates a 0.5 to 150 MHz phase-locked loop PLL

Contextual Info: ANALOG DEVICES DSP Microcomputer ADSP-2186L FEATURES PERFORMANCE 30 ns Instruction Cycle Tim e 33 MIPS Sustained Performance Single-Cycle Instruction Execution Single-Cycle C ontext Switch 3-Bus Architecture Allow s Dual Operand Fetches in Every Instruction Cycle

CL 2181 ic

Abstract: C6p ad ADSP-2181 ez-kit free software ADSP2181 boot
Contextual Info: ANALOG DEVICES C6P Mcrocorrputer O T -2181 FEATURES PERFORMANCE 25 ns Instruction Cycle Tim e from 20 M Hz Crystal @ 5.0 Volts 40 MIPS Sustained Performance Single-Cycle Instruction Execution Single-Cycle Context Switch 3-Bus Architecture Allow s Dual Operand Fetches in

24M quartz crystal

Abstract: LXMS 31 009 LXMS 31 011 quartz 24M 1AD4 001C ADSP-2100 ADSP-2181 ADSP-2189M 0x0000-0x1FFF
Contextual Info: ANALOG DEVICES FEATURES PERFORMANCE 13.3 ns Instruction Cycle Tim e @ 2.5 V olts Internal , 75 MIPS Sustained Performance Single-Cycle Instruction Execution Single-Cycle Context Switch 3-Bus Architecture Allow s Dual Operand Fetches in Every Instruction Cycle

0x2000a

Contextual Info: ANALOG DEVICES □ Preliminary Technical Data DSP Microcomputer ADSP-2189M FEATURES Performance 13.3 ns Instruction Cycle Tim e @ 2.5 Volts internal , 75 M IPS Sustained Performance Single-Cycle Instruction Execution Single-Cycle C ontext Switch 3-Bus A rchitecture Allows D ual O perand Fetches in Every Instruction Cycle

CL 2181 ic

Abstract: AT/CL 2181 ic CL 2181
Contextual Info: ANALOG DEVICES DSP Microcomputers ADSP-2181 /ADSP-2183 FEATURES PERFORMANCE 30 ns Instruction Cycle Time @ 5.0 Volts 33 MIPS Sustained Performance 34.7 ns Instruction Cycle Time @ 3.3 Volts Single-Cycle Instruction Execution Single-Cycle Context Switch 3-Bus Architecture Allows Dual Operand Fetches in

sp2111

Abstract: SP-2111 plc analog em 231 ADSP-2115-BP-55 marking YJ AM marking code BM 68A
Contextual Info: ANALOG DEVICES □ ADSP-2100 Family DSP Microcomputers ADSP-21 xx FUNCTIONAL BLOCK DIAGRAM SUMMARY 16-Bit Fixed-Point DSP Microprocessors with On-Chip Memory Enhanced Harvard Architecture for Three-Bus Performance: Instruction Bus & Dual Data Buses Independent Computation Units: ALU, Multiplier/

Contextual Info: ANALOG DEVICES Preliminary Technical Data FEATURES PERFORMANCE 25 ns Instruction Cycle Tim e 40 MIPS Sustained Performance Single-Cycle Instruction Execution Single-Cycle Context Switch 3-Bus Architecture A llow s Dual Operand Fetches in Every Instruction Cycle

Contextual Info: ANALOG DEVICES FEATURES PERFORMANCE 25 ns Instruction Cycle Tim e 40 MIPS Sustained Performance Single-Cycle Instruction Execution Single-Cycle Context Switch 3-Bus Architecture A llow s Dual Operand Fetches in Every Instruction Cycle M ultifunction Instructions

klb x5

Abstract: digital modem v.92 v.90 EZ 711 253 ST EZ 711 253 "analog devices" adsp 2181 modem* 56k "analog devices" adsp 2181 modem* v.34 ADSP-2100 ADSP-2181 LU110 "analog devices" adsp 2181 modem
Contextual Info: Multiport Internet Gateway Processor ADSP-21mod970 ANALOG DEVICES FEATURES PERFORMANCE Complete Single-Chip Multiport Internet Gateway Processor No External Mem ory Required Implements Six Modem Channels in One Package Each Processor Can Implement V.34/V.90 Data/Fax

Contextual Info: 32-BIT AND 64-BIT IEEE FLOATING-POINT MULTIPLIER AND ALU DESCRIPTION: FEATURES: T h e IDT721264 flo a tin g -p o in t m u ltip lie r and the IDT721265 flo a tin g -p o in t ALU p ro v id e h ig l^ p e e d 3 2-b it and 64-bit flo a tin g ­ p o in t p ro c e s s in g ca p a b ility .

Geest

Abstract: ansoft hfss Pennsylvania Model 7600 PIN diode SPICE model Schematic convolution interleaving sharp lm1 spice h/BC517 spice model
Contextual Info: DesignCon 2004 Making S-parameter data suitable for SPICE modeling Jan De Geest, Ph.D, FCI CDC Stefaan Sercu, Ph.D, FCI CDC Craig Clewell, FCI CDC Jim Nadolny, FCI CDC FCI Communications, Data, Consumer Division FCI ‘s-Hertogenbosch Victorialaan 1, 5213 JG ’s-Hertogenbosch,

BM 1313

Contextual Info: POSIIRONIC M D U SIR ES BEUEVES THE DM A ON TH E DRNMNQ TO B E RELIABLE. 9N C E THE TECHMCAL INFORMATION IS GIVEN FREE OF CHARGE, THE USER EMPLOYS SUCH MFORMMION AT H B OWN D6CRED0N ANO RISK. POSTTROMC MOUSTRIES ASSUM ES NO RESPO NSaUTY FOR RESULTS O BM N ED OR DAMAGES

CW030F-M

Abstract: CW030C TN97-015EPS cw030f CW030A CW030A-M CW030B 8852c CW030C-M
Contextual Info: Data Sheet April 2008 CW030-Series Power Modules; dc-dc Converters: 36 Vdc to 75 Vdc Inputs; 30 W Features n The CW030-Series Power Modules use advanced, surfacemount technology and deliver high-quality, compact, dc-dc conversion at an economical price. Applications

Contextual Info: Data Sheet April 2008 CW030-Series Power Modules; dc-dc Converters: 36 Vdc to 75 Vdc Inputs; 30 W Features n The CW030-Series Power Modules use advanced, surfacemount technology and deliver high-quality, compact, dc-dc conversion at an economical price. Applications

1AD4

Abstract: 001C A0-A21 AD1847 ADSP-2100 ADSP-2181 ADSP-2184L
Contextual Info: ANALOG DEVICES FEATURES PERFORMANCE 25 ns Instruction Cycle Tim e 40 MIPS Sustained Performance Single-Cycle Instruction Execution Single-Cycle Context Switch 3-Bus Architecture A llow s Dual Operand Fetches in Every Instruction Cycle M ultifunction Instructions

SK5253

Contextual Info: SK5253 POSIIRONIC M D U SIR ES BELEVES THE DM A ON TH E DRMMNO TO B E RELIABLE. SINCE THE TECHMCAL MFORMATION IS GIVEN FREE OF CHARGE. THE USER EMPLOYS SUCH INFORMATION AT M S OWN DISCRETION AND R6K. PO STRONB INDUSTRIES ASSUM ES NO R ESPO N SaU IY FOR RESULTS O BM N ED OR D M IM E S

Contextual Info: Picture cell driver for STN LCD driver for low voltage power supplies BU9718KV The BU9718KV is a driver !C designed for the character-type STN liquid crystal p an ics w hich are idea! for applica­ tions such as portable d evices. The num ber of display segm ents includes 32 output segm ents and 3 common out­

Contextual Info: a FEATURES PERFORM ANCE 25 ns Instruction Cycle Time from 20 M Hz Crystal @ 5.0 Volts 40 M IPS Sustained Performance Single-Cycle Instruction Execution Single-Cycle Context Sw itch 3-Bus Architecture Allow s Dual Operand Fetches in Every Instruction Cycle

Contextual Info: SK6644 REVISION RECORD ECO 2 4 8 6 1 DATE REV 10-14 06 NC POSnRONIC M D U SIR ES BELEVES THE DM A ON TH E DRAWING TO BE RELIABLE. SINCE THE TECHMCAL M FORMATION IS GIVEN FREE OF CHARGE. THE USER EM P10I5 SUCH INFORMATION AT M S OWN DISCRETION AND R6K. P06TTR0MC INDUSTRIES ASSUM ES NO

SCC68910

Abstract: NL C6J 68000 mmu 68451 scc68 scc681 D-10 PA21 J10H "memory access controller" and signetics and 68000
Contextual Info: Signetics SCC68905 Basic Memory Access Controller BMAC Preliminary Specification Microprocessor Products DESCRIPTION PIN CONFIGURATION T h e Signetics S C C 6 8 9 0 5 Basic Mem ory A ccess Controller (B M A C ) is designed for the S 6 8 0 0 0 family (6 80 0 0 , 6 8 0 1 0 and