BMODE16 Search Results

MB86860

Abstract: 0x80000410 bit3113 SCSN1 sparclite hypersparc BIT3115 S200 SS200 SAD-100
Contextual Info: MB86860 SPARClite SPARClite MB86860 Series Data Sheet Rev.1.2 July 27, 1999 Fujitsu This material is preliminary and is subject to change without notice.  SPARC is a registered trademark of SPARC International, Inc. in the United States and is based on technology developed by Sun

0x00000000-0x00007FF

Abstract: mb86833 MB86930 0x00000148 sparclite asi bus DRAM controller MB86832
Contextual Info: SPARClite 830 Series Embedded Processor User’s Manual MB86833 OCTOBER 1997, Edition 1.0 FUJITSUMICROELECTRONICS, INC. CONTENTS Chapter 1: Overview of MB86833 1.1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

0x000001D8

Abstract: sparclite fujitsu dot matrix printer circuit diagram monitor e74 0x00000128 MB86930 IS 208 MXM pin assignment E5214 e328
Contextual Info: SPARClite 930 Series Embedded Processor User’s Manual MB86936 Addendum JULY 1996, Edition 1.3 FUJITSUMICROELECTRONICS, INC. SPARClite User’s Manual – MB86936 Addendum Overview of the MB86936 1 Caches 2 Bus Interface Unit 3 DRAM Controller 4 DMA Controller

Contextual Info: MB86833 SPARCIite SERIES 32-BIT RISC EMBEDDED PROCESSOR FUJITSU DATASHEET MARCH 1998 FEATURES Programmable address decoder and wait-state genera­ tor Single vector trapping • 66 M Hz CPU with on-chip clock multiplier 0.35 micron gate, 2-level metal CMOS technology,

Contextual Info: ASSP CMOS SPARCIite Series 32-Bit RISC Embedded Processor MB86833 Package • 144-pin, Plastic LQFP • FPT-144-M 08 Features 66 MHz CPU w ith on-chip clock m ultiplier Bus interface support for 8-, 16-, or 32-bit wide memory SPARC high performance RISC architecture

Contextual Info: MB86935 Bus Interface Unit H3.1 Overview of Bus Interface Unit The BIU on the MB86935 includes all the features of the MB86930, and in addition offers the following: • Option to run core at double the frequency of the Bus Interface Unit, • Four-word burst mode for instruction fetches and data loads,

Contextual Info: ASSP CMOS SPARCIite Series 32-Bit RISC Embedded Processor MB86831 Package • 176-pin, Plastic SQFP • FPT-176P-M01 Features 66 or 80 MHz CPU with on-chip clock multiplier Bus interface support for 8-, 16-, or 32-bit wide memory SPARC high performance RISC architecture

MARKING cfk

Abstract: marking code CFK MB86936A
Contextual Info: MB86936 FUJITSU 930 SERIES 32-BIT RISC EMBEDDED PROCESSOR AUGUST, 1996 • • • • JTAG test interface Emulator support hardware Single vector trapping Power down modes, with global or selective power down • 0.5 micron gate, 3 level metal CMOS technology,

Contextual Info: MB86932 FUJITSU SPARCIite 32-BIT RISC EMBEDDED PROCESSOR MAY 25, 1994 FEATURES • 4 0 M H z 2 5 n s/cy cle operating frequency • SPARC high perform ance R IS C architecture • 8 K by tes 2 -way set associative instruction cach e • 2 K bytes 2 - way set associative data cache

MB86986

Abstract: IEEE754 MB86930 0x00001000
Contextual Info: SPARClite MB86930 TO MB86936 MIGRATION APPLICATION NOTE 5 FUJITSU MICROELECTRONICS, INC. REVISION 01 APPLICATION NOTE 5 INTRODUCTION ification, and the SPARC IEEE754 Implementation Recommendation with the Nonstandard FP NS=1 mode enabling “flush to zero” treatment of denormalized operands or results as permitted by the recommendation.

sparclite

Abstract: MB86833 ADR11 ADR14 MB86833PFV-G bit3116 MB8683X
Contextual Info: ASSP CMOS SPARClite Series 32-Bit RISC Embedded Processor MB86833 Package • 144-pin, Plastic LQFP • FPT-144-M08 Features • 66 MHz CPU with on-chip clock multiplier • Bus interface support for 8-, 16-, or 32-bit wide memory • SPARC high performance RISC architecture

t20s

Abstract: SQFP208 MB86930 MB86936A
Contextual Info: MB86936 930 SERIES 32–BIT RISC EMBEDDED PROCESSOR AUGUST, 1996 • JTAG test interface FEATURES • Emulator support hardware • 50 MHz version with clock doubling • SPARC high performance RISC architecture • High Performance SPARC FPU, ANSI/IEEE 754

SPARC v8 architecture BLOCK DIAGRAM

Abstract: G545 MB86930 G514 0101 g547
Contextual Info: SPARClite 930 Series Embedded Processor User’s Manual MB86933H Addendum JULY 1996, EDITION 1.0 FUJITSU MICROELECTRONICS, INC. Overview of the MB86933H 1 Programmer’s Model 2 Internal Architecture 3 MB86933H Interrupt Request Controller 4 External Interface

sparclite

Abstract: 0x00000000-0x00007FF MB86930 asi bus MB86831 darm DRAM controller 0x00000154
Contextual Info: SPARClite 830 Series Embedded Processor User’s Manual MB86831 MAY 1997, Edition 1.0 FUJITSUMICROELECTRONICS, INC. SPARClite User’s Manual - MB86831 Overview of the MB86831 1 Caches 2 Bus Interface Unit 3 DRAM Controller with EDO DRAM Support 4 Interrupt Request Controller

Contextual Info: MB86831 FUJITSU S P A R C Iite S E R IE S 3 2 -B IT R IS C E M B E D D E D P R O C E S S O DATA S H E E T FE B R U A R Y 199 Built-in Internal Clock frequency multiplier circuit FEATURES Single vector trapping 66MH/., 80MHz and 100 MHz. versions each with

Contextual Info: C h apter 3 MB86831 Bus Interface Unit 3.1 Overview of Bus Interface Unit The BIU on the MB86831 offers the following features: • Option to run core at multiplied frequency of the Bus Interface Unit, xl, x2, x3, x4. • Four-word burst mode for instruction fetches and data loads,

Contextual Info: SPARCIite Series 32-Bit RISC Embedded Processor MB86832 Package • 176-pin, Plastic SQFP • FPT-176P-M01 • 66, 80, or 100 MHz CPU with on-chip clock multiplier Bus interface support for 8-, 16-, or 32-bit wide memory • SPARC high performance RISC architecture

b2675

Abstract: bit310 hypersparc 0x80000108
Contextual Info: MB86860 SPARClite SPARClite MB86860 Preliminary Data Sheet Rev.1.0 May 1, 1999 Fujitsu This material is preliminary and is subject to change without notice. SPARC is a registered trademark of SPARC International, Inc. in the United States and is based on technology developed by Sun

OX520

Contextual Info: I MB86934_ FUJITSU 930 Series 32-BIT RISC EMBEDDED PROCESSOR June 1996 FEATURES GENERAL DISCUSSION • 50 MHz operating frequency, 40 MHz operating fre­ quency when FIFO is used • SPARC* high performance RISC architecture • High Performance SPARC FPU, ANSI/IEEE 754

2AP10

Contextual Info: ASSP CMOS SPARClite Series 32-Bit RISC Embedded Processor MB86831 Package ¥ 176-pin, Plastic SQFP ¥ FPT-176P-M01 Features • 66 or 80 MHz CPU with on-chip clock multiplier • Bus interface support for 8-, 16-, or 32-bit wide memory • SPARC high performance RISC architecture

Contextual Info: ASSP CMOS SPARClite Series 32-Bit RISC Embedded Processor MB86832 Package ¥ 176-pin, Plastic SQFP ¥ FPT-176P-M01 Features • 66, 80, or 100 MHz CPU with on-chip clock multiplier • Bus interface support for 8-, 16-, or 32-bit wide memory • SPARC high performance RISC architecture

tag 8534

Abstract: TAG 8537 ps0001
Contextual Info: MB86860 Series Hardware Manual SPARClite MB86860 Series Hardware Manual Edition 1.1 - Jul. 29, 1999 Fujitsu Ltd Rev.1.1 Jul.29/’99 - Fig 8-3 of Page 8-10 and Fig.8-4 of Page 8-11 DQ32, 33, 33, 34, …, 62 => DQ32, 33, 34, 35, …, 63 - Page 8-12 Note is added.

Contextual Info: C h a pter 3 MB86832 Bus Interface Unit 3.1 Overview of Bus Interface Unit The BIU on the MB86832 offers the following features: • Option to run core at multiplied frequency of the Bus Interface Unit, x l, x2, x3, x4. • Four-word burst mode for instruction fetches and data loads,

g545

Contextual Info: R iB b I i i i i i i i i i i i i i i External Interface The processor external interface consists of signals for bus operations and for system control. This chapter details the MB86933H signal set, describes basic bus timing, and describes the programmable wait-state generator, on-chip timer, and same-page