CD74HC112 |
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Texas Instruments
|
High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Set and Reset |
|
Original |
PDF
|
43.47KB |
8 |
CD74HC112 |
|
Texas Instruments
|
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger |
|
Original |
PDF
|
54.05KB |
8 |
CD74HC112E |
|
Texas Instruments
|
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger |
|
Original |
PDF
|
54.05KB |
8 |
CD74HC112E |
|
Texas Instruments
|
High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Set and Reset 16-PDIP -55 to 125 |
|
Original |
PDF
|
650.43KB |
18 |
CD74HC112E |
|
Texas Instruments
|
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger |
|
Original |
PDF
|
234.56KB |
13 |
CD74HC112E |
|
Texas Instruments
|
CD74HC112 - High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Set and Reset 16-PDIP -55 to 125 |
|
Original |
PDF
|
774.28KB |
20 |
CD74HC112E |
|
Harris Semiconductor
|
Dual J-K Flip-Flop with Set and Reset |
|
Scan |
PDF
|
432.86KB |
5 |
CD74HC112E |
|
Unknown
|
Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. |
|
Historical |
PDF
|
32.93KB |
1 |
CD74HC112E96 |
|
Texas Instruments
|
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger |
|
Original |
PDF
|
41.05KB |
8 |
CD74HC112EE4 |
|
Texas Instruments
|
High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Set and Reset |
|
Original |
PDF
|
373.18KB |
15 |
CD74HC112EE4 |
|
Texas Instruments
|
High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Set and Reset 16-PDIP -55 to 125 |
|
Original |
PDF
|
650.43KB |
18 |
CD74HC112EE4 |
|
Texas Instruments
|
CD74HC112 - High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Set and Reset 16-PDIP -55 to 125 |
|
Original |
PDF
|
774.28KB |
20 |
CD74HC112H |
|
Harris Semiconductor
|
Dual J-K Flip-Flop with Set and Reset |
|
Scan |
PDF
|
432.86KB |
5 |
CD74HC112M |
|
Harris Semiconductor
|
Dual J-K Flip-Flop with Set and Reset |
|
Scan |
PDF
|
432.86KB |
5 |
|
CD74HC112M96 |
|
Texas Instruments
|
High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Set and Reset 16-SOIC -55 to 125 |
|
Original |
PDF
|
650.43KB |
18 |
CD74HC112M96 |
|
Texas Instruments
|
HIGH SPEED CMOS LOGIC DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH SET AND RESET |
|
Original |
PDF
|
54.05KB |
8 |
CD74HC112M96 |
|
Texas Instruments
|
CD74HC112 - High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Set and Reset 16-SOIC -55 to 125 |
|
Original |
PDF
|
774.28KB |
20 |
CD74HC112M96 |
|
Unknown
|
Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. |
|
Historical |
PDF
|
32.93KB |
1 |
CD74HC112M96E4 |
|
Texas Instruments
|
High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Set and Reset |
|
Original |
PDF
|
373.18KB |
15 |
CD74HC112M96E4 |
|
Texas Instruments
|
High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Set and Reset 16-SOIC -55 to 125 |
|
Original |
PDF
|
650.43KB |
18 |