CHN 639 Search Results

ST CHN 510

Abstract: 83C97 chn 809 chn 809 ST
Contextual Info: 83C97 T e chn o log y, In co rp o rate d 10BASE-T Ethernet Transceiver With On Chip Filters and Digital Interface and Serial Port PRELIMINARY October 1994 SEEQ AutoDUPLEX Designation S ym bol indentifies product as A u to D U P L E X device. Description

chn 809

Abstract: chn 809 ST Transistor TT 2246 transistor chn 037 MO40 TT 2246 transistor capacitor JA8 KMA Series 232 pin diagram of BC 547 SABRE 408
Contextual Info: 83C95 T e chn o log y, Inco rp o rate d 10BASE-T Ethernet Transceiver With On Chip Filters And AUI PRELIMINARY October 1994 S E E Q A u to D U P L E X D esignation Symbol indentifies product as AutoDUPLEX device. D escription The 83C95 is a highly integrated analog interface 1C for

Transistor TT 2246

Abstract: transistor chn 911 TT 2246 transistor jm31a pulse electronics era transformer transistor chn 037 chn 809 S4744
Contextual Info: SEEQ T e chn o log y, Inco rp o rate d 83C96 10BASE-T Ethernet Transceiver With On Chip Filters and Digital Interface PRELIMINARY October 1994 SEEQ AutoDUPLEX Designation Sym bol indentifies product as A u to D U P L E X device. Description The 83C96 is a highly integrated analog interface 1C for

CHN 550

Abstract: CHN 545 chn 710 CHN 712 chn 538 CHN 431 CHN 709 CHN 741 chn 738 chn 648 equivalent
Contextual Info: R&S ZNC/ZND Vector Network Analyzers User Manual ;xíÇ2 User Manual Test & Measurement 1173.9557.02 ─ 26 This manual describes the following vector network analyzer types: ● R&S®ZNC3 (2 ports, 9 kHz to 3 GHz, N connectors), order no. 1311.6004K12

Contextual Info: 80C24 Technology Incorporated AutoDUPLEX CMOS Ethernet Interface Adapter PRELIMINARY DATA SHEET December 10, 1996 Functional Features • Low Power CMOS Technology Ethernet Serial Note: Check for latest Data Sheet revision before starting any designs. Interface Adapter with Integrated Manchester

M2KA

Abstract: HEPC XS2F-D523-D80-A OMR H C3JW ly2f t2 YAZAKI Terminal7116-4022 WL01CA 54151A
Contextual Info: We surveyed SVHC 161 substances. REACH/SVHC Information Product description SMCI XB. SMC TE SENSOR YA-JA01 PB FREE SENSOR YA-HC05 PBFREE SP SMC DI SENSOR YA-HC04 SMC DI SENSOR YA-JB01 SENSOR YA-HC09(SP) SENSOR YA-HA01PB-FREE(SP) SENSOR YA-HC09 SMC YA-JA02 A-TE SENSOR

CHN b42

Abstract: chn 743 pin of chn 743 chn 529 CHN 524 chn 729 CHN 849 CHN 616 CHN 847 RYM 17-18
Contextual Info: ADSP-21065L SHARC DSP Technical Reference Revision 2.0, July 2003 Part Number 82-001903-01 Analog Devices, Inc. One Technology Way Norwood, Mass. 02062-9106 a Copyright Information 2003 Analog Devices, Inc., ALL RIGHTS RESERVED. This document may not be reproduced in any form without prior, express written consent

processor cross reference

Abstract: DATASHEET OF DMA dma controller ADSP-21065 ADSP-21065L CHN 643 CHN 632 CHN 617 CHN 616 CHN 642
Contextual Info:  '0$ Figure 6-0. Listing 6-0. Table 6-0. Table 6-0. Direct Memory Access DMA provides a mechanism for transferring an entire block of data. The processor’s on-chip DMA controller relieves the core processor of moving data between internal memory and an external data source or

CHN 648

Abstract: chn 542 CHN 612 diode CHN 552 CHN 628 CHN 522 CHN 632 chn 637 chn 621 CHN 631
Contextual Info: XRT86L38 PRELIMINARY PRELIMINARY OCTAL T1/E1/J1 FRAMER/LIU COMBO JUNE 2004 REV. P1.1.5 GENERAL DESCRIPTION The XRT86L38 is an eight-channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated solution featuring R3 technology Relayless, Reconfigurable, Redundancy . The physical interface is optimized with internal impedance, and with the patented pad structure, the XRT86L38 provides protection

CHN 612 diode

Abstract: CHN 545 CHN 648 chn 542 CHN 519 ST chn 624 CHN 507 SCR PIN CONFIGURATION CHN 035 CHN 522 CHN 535
Contextual Info: áç XRT86L38 PRELIMINARY PRELIMINARY OCTAL T1/E1/J1 FRAMER/LIU COMBO AUGUST 2004 REV. P1.1.6 GENERAL DESCRIPTION The XRT86L38 is an eight-channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated solution featuring R3 technology Relayless, Reconfigurable, Redundancy . The physical interface is optimized with internal impedance, and with the patented pad structure, the XRT86L38 provides protection

chn 924

Abstract: chn 648 equivalent
Contextual Info: XRT86L38 PRELIMINARY PRELIMINARY OCTAL T1/E1/J1 FRAMER/LIU COMBO JUNE 2004 REV. P1.1.3 GENERAL DESCRIPTION The XRT86L38 is an eight-channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated solution featuring R3 technology Relayless, Reconfigurable, Redundancy . The physical interface is optimized with internal impedance, and with the patented pad structure, the XRT86L38 provides protection

chn 924

Abstract: CHN 643 144T1 CHN G4 120 chn 648 equivalent 1/CHN 545
Contextual Info: XRT86L38 PRELIMINARY PRELIMINARY OCTAL T1/E1/J1 FRAMER/LIU COMBO MAY 2004 REV. P1.1.1 GENERAL DESCRIPTION The XRT86L38 is an eight-channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated solution featuring R3 technology Relayless, Reconfigurable, Redundancy . The physical interface is optimized with internal impedance, and with the patented pad structure, the XRT86L38 provides protection

CHN G4 141

Contextual Info: XRT86L38 PRELIMINARY PRELIMINARY OCTAL T1/E1/J1 FRAMER/LIU COMBO APRIL 2004 REV. P1.1.0 GENERAL DESCRIPTION The XRT86L38 is an eight-channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated solution featuring R3 technology Relayless, Reconfigurable, Redundancy . The physical interface is optimized with internal impedance, and with the patented pad structure, the XRT86L38 provides protection

CHN G4 309

Abstract: 40 serice free DMO 565 R CHN 932
Contextual Info: xr XRT86L38 PRELIMINARY OCTAL T1/E1/J1 FRAMER/LIU COMBO JANUARY 2005 REV. P1.1.7 GENERAL DESCRIPTION The XRT86L38 is an eight-channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated solution featuring R3 technology Relayless, Reconfigurable, Redundancy .

CHN 932

Contextual Info: XRT86L34 PRELIMINARY PRELIMINARY QUAD T1/E1/J1 FRAMER/LIU COMBO APRIL 2004 REV. P1.1.0 GENERAL DESCRIPTION The XRT86L34 is a four-channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated solution featuring R3 technology Relayless, Reconfigurable, Redundancy . The physical interface is optimized with internal impedance, and with the patented pad structure, the XRT86L34 provides protection

DMO 565 R

Abstract: CHN 652 CHN 933 chn 539 W0104 CHN 628 CHN 523 chn 648 equivalent 3667 ict XRT86L34IB
Contextual Info: XRT86L34 PRELIMINARY PRELIMINARY QUAD T1/E1/J1 FRAMER/LIU COMBO MAY 2004 REV. P1.1.1 GENERAL DESCRIPTION The XRT86L34 is a four-channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated solution featuring R3 technology Relayless, Reconfigurable, Redundancy . The physical interface is optimized with internal impedance, and with the patented pad structure, the XRT86L34 provides protection

DMO 565 R

Abstract: chn 656 chn 637 chn 547 CHN 549 dmo 265 CHN 922 equivalent CHN 632 CHN 645 chn 648 equivalent
Contextual Info: XRT86L34 PRELIMINARY PRELIMINARY QUAD T1/E1/J1 FRAMER/LIU COMBO JUNE 2004 REV. P1.1.3 GENERAL DESCRIPTION The XRT86L34 is a four-channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated solution featuring R3 technology Relayless, Reconfigurable, Redundancy . The physical interface is optimized with internal impedance, and with the patented pad structure, the XRT86L34 provides protection

philips I2S bus specification

Abstract: I2S serial bus protocol Inter-ICs AES/EBU transceiver Digital Audio Transmitters Audio Transmitters ADSP-2165L 21065L-EZ-LAB AC97 chn 639
Contextual Info: a Application Note Interfacing I2S-Compatible Audio Devices To The ADSP-21065L Serial Ports SDRAM Host Micro a a 2 Channel D/A 2 Channel D/A ADSP 21065L 2 Channel D/A 2 Channel D/A Version 1.0A John Tomarakos ADI DSP Applications 4/2/99 0. Introduction The ADSP-21065L is the newest first generation SHARC member to be released, enabling 32-bit processing in either fixed or

SDH 209

Abstract: DMO 565 R SCR PIN CONFIGURATION CHN 035 CHN G4 309 telephone schemes sa8316 dmo 265 CHN G4 329
Contextual Info: xr XRT86VL38 PRELIMINARY OCTAL T1/E1/J1 FRAMER/LIU COMBO MARCH 2005 REV. P1.0.6 GENERAL DESCRIPTION The XRT86VL38 is an eight-channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated solution featuring R3 technology Relayless, Reconfigurable, Redundancy .

dmo 565 r

Abstract: CHN 522 chn 542 chn 621 CHN 616 CHN 507 chn 638 chn 537 chn 543 CHN 618
Contextual Info: xr XRT86VL32 PRELIMINARY PRELIMINARY DUAL T1/E1/J1 FRAMER/LIU COMBO SEPTEMBER 2004 REV. P1.0.1 GENERAL DESCRIPTION The XRT86VL32 is a two-channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated solution featuring R3 technology Relayless, Reconfigurable, Redundancy . The physical interface is optimized with internal impedance, and with the patented pad structure, the XRT86VL32 provides protection

rx1a 1244

Abstract: CHN 616 ice 8040 ADSP-21065L h 945 p 4000 CMOS texas instruments 0x200014 F15-F8 PM48 multi timer Chn 835
Contextual Info: ADSP-21065L SHARC DSP User’s Manual Revision 2.0, July 2003 Part Number 82-001833-01 Analog Devices, Inc. One Technology Way Norwood, Mass. 02062-9106 a Copyright Information 2003 Analog Devices, Inc., ALL RIGHTS RESERVED. This document may not be reproduced in any form without prior, express written consent

mdd 2605

Abstract: HCPL 1458 8 pin opto KS0108 128X64 graphical LCD mdd 2601 transistor chn 952 hitachi INVC 618 Data Vision P135 H4 led smd headlight bulb transistor CHN 64 946 transistor chn 943
Contextual Info: 755 Technical portal and online community for Design Engineers - www.element-14.com Optoelectronics, Solid State Illumination & Displays Page Alphanumeric LCD Modules . . . . . . . . . . . . . . . . . 903 Alphanumeric LED Displays . . . . . . . . . . . . . . . . . 900

chn 817

Contextual Info: Dual-Channel, 14-Bit, CCD Signal Processor with Precision Timing Core AD9974 FEATURES GENERAL DESCRIPTION 1.8 V analog and digital core supply voltage Correlated double sampler CDS with −3 dB, 0 dB, +3 dB, and +6 dB gain 6 dB to 42 dB, 10-bit variable gain amplifier (VGA)

chn 817

Abstract: chn 809 CHN 816 chn 807 chn 80B scp3 3h3 chn 037 AD9974
Contextual Info: Dual-Channel, 14-Bit, CCD Signal Processor with Precision Timing Core AD9974 FEATURES GENERAL DESCRIPTION 1.8 V analog and digital core supply voltage Correlated double sampler CDS with −3 dB, 0 dB, +3 dB, and +6 dB gain 6 dB to 42 dB, 10-bit variable gain amplifier (VGA)