ADSP-21160
Abstract: KLS65
Text: DSP Microcomputer ADSP-21160 Preliminary Technical Data 6800$5< . < ($785(6 y r a n i l m a i l c i e Pr chn a Te Dat DUAL-PORTED SRAM CORE PROCESSOR TIMER INSTRUCTION CACHE TWO INDEPENDENT DUAL-PORTED BLOCKS 32 x 48-BIT
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ADSP-21160
48-BIT
8x4x32
/236SHDNDQG0
63LVWREHGHWHUPLQHG
ADSP-21160
KLS65
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CHN 550
Abstract: CHN 545 chn 710 CHN 712 chn 538 CHN 431 CHN 709 CHN 741 chn 738 chn 648 equivalent
Text: R&S ZNC/ZND Vector Network Analyzers User Manual ;xíÇ2 User Manual Test & Measurement 1173.9557.02 ─ 26 This manual describes the following vector network analyzer types: ● R&S®ZNC3 (2 ports, 9 kHz to 3 GHz, N connectors), order no. 1311.6004K12
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6004K12
ZNC-B10
ZN-B14
ZNC-B19
ZNC3-B22
ZNC-K19
VXI-11
CHN 550
CHN 545
chn 710
CHN 712
chn 538
CHN 431
CHN 709
CHN 741
chn 738
chn 648 equivalent
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Digital Alarm Clock using 8051
Abstract: chn 448 chn 706 CHN 632 CHN 703 RAM 2112 256 word 32.768mhz pin hole thru chn 608 microcontroller 8051 application of alarm clock octal tri state buffer ic
Text: áç XRT84L38 OCTAL T1/E1/J1 FRAMER FEBRUARY 2004 REV. 1.0.0 GENERAL DESCRIPTION The XRT84L38 is an eight-channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framing controller. The XRT84L38 contains an integrated DS1/E1/J1 framer which provides DS1/E1/J1 framing and error accumulation in accordance with ANSI/ITU_T specifications.
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XRT84L38
XRT84L38
Digital Alarm Clock using 8051
chn 448
chn 706
CHN 632
CHN 703
RAM 2112 256 word
32.768mhz pin hole thru
chn 608
microcontroller 8051 application of alarm clock
octal tri state buffer ic
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CHN G4 136
Abstract: chn7 SA8 357 TR54016 XRT83L38 XRT84L38 XRT84L38IB 7174B 8ch LOW SATURATION DRIVER C1-168
Text: XRT84L38 OCTAL T1/E1/J1 FRAMER SEPTEMBER 2006 REV. 1.0.1 GENERAL DESCRIPTION The XRT84L38 is an eight-channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framing controller. The XRT84L38 contains an integrated DS1/E1/J1 framer which provides DS1/E1/J1 framing and error
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XRT84L38
XRT84L38
CHN G4 136
chn7
SA8 357
TR54016
XRT83L38
XRT84L38IB
7174B
8ch LOW SATURATION DRIVER
C1-168
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CHN G4 124
Abstract: CHN G4 329
Text: áç XRT84L38 PRELIMINARY OCTAL T1/E1/J1 FRAMER JULY 2003 REV. P1.0.4 GENERAL DESCRIPTION The XRT84L38 is an eight-channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framing controller. The XRT84L38 contains an integrated DS1/E1/J1 framer which provides DS1/E1/J1 framing and error accumulation in accordance with ANSI/ITU_T specifications.
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XRT84L38
XRT84L38
CHN G4 124
CHN G4 329
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rbs 6201 manual
Abstract: rbs 6201 POWER CONSUMPTION chn 452 rbs 6201 specification chn 710 SCR PIN CONFIGURATION CHN 035 RBS 6201 INFORMATION SDH 209 rbs 6201 LOP 36 AF
Text: XRT86L38 PRELIMINARY PRELIMINARY OCTAL T1/E1/J1 FRAMER/LIU COMBO NOVEMBER 2003 REV. P1.0.4 GENERAL DESCRIPTION The XRT86L38 is an eight-channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated solution. The XRT86L38 contains an integrated DS1/
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XRT86L38
XRT86L38
TR54016,
G-703,
rbs 6201 manual
rbs 6201 POWER CONSUMPTION
chn 452
rbs 6201 specification
chn 710
SCR PIN CONFIGURATION CHN 035
RBS 6201 INFORMATION
SDH 209
rbs 6201
LOP 36 AF
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add 2201
Abstract: l 7135 MOTOROLA MP
Text: XRT86L34 PRELIMINARY QUAD T1/E1/J1 FRAMER/LIU COMBO NOVEMBER 2003 REV. P1.0.2 GENERAL DESCRIPTION The XRT86L34 is a four-channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated solution. The XRT86L34 contains an integrated DS1/ E1/J1 framer and LIU which provide DS1/E1/J1 framing and error accumulation in accordance with ANSI/
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XRT86L34
XRT86L34
add 2201
l 7135
MOTOROLA MP
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CHN 648
Abstract: chn 542 CHN 612 diode CHN 552 CHN 628 CHN 522 CHN 632 chn 637 chn 621 CHN 631
Text: XRT86L38 PRELIMINARY PRELIMINARY OCTAL T1/E1/J1 FRAMER/LIU COMBO JUNE 2004 REV. P1.1.5 GENERAL DESCRIPTION The XRT86L38 is an eight-channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated solution featuring R3 technology Relayless, Reconfigurable, Redundancy . The physical interface is optimized with internal impedance, and with the patented pad structure, the XRT86L38 provides protection
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XRT86L38
XRT86L38
CHN 648
chn 542
CHN 612 diode
CHN 552
CHN 628
CHN 522
CHN 632
chn 637
chn 621
CHN 631
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CHN 612 diode
Abstract: CHN 545 CHN 648 chn 542 CHN 519 ST chn 624 CHN 507 SCR PIN CONFIGURATION CHN 035 CHN 522 CHN 535
Text: áç XRT86L38 PRELIMINARY PRELIMINARY OCTAL T1/E1/J1 FRAMER/LIU COMBO AUGUST 2004 REV. P1.1.6 GENERAL DESCRIPTION The XRT86L38 is an eight-channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated solution featuring R3 technology Relayless, Reconfigurable, Redundancy . The physical interface is optimized with internal impedance, and with the patented pad structure, the XRT86L38 provides protection
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XRT86L38
XRT86L38
CHN 612 diode
CHN 545
CHN 648
chn 542
CHN 519
ST chn 624
CHN 507
SCR PIN CONFIGURATION CHN 035
CHN 522
CHN 535
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chn 924
Abstract: chn 648 equivalent
Text: XRT86L38 PRELIMINARY PRELIMINARY OCTAL T1/E1/J1 FRAMER/LIU COMBO JUNE 2004 REV. P1.1.3 GENERAL DESCRIPTION The XRT86L38 is an eight-channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated solution featuring R3 technology Relayless, Reconfigurable, Redundancy . The physical interface is optimized with internal impedance, and with the patented pad structure, the XRT86L38 provides protection
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XRT86L38
XRT86L38
TR54016,
G-703,
chn 924
chn 648 equivalent
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chn 924
Abstract: CHN 643 144T1 CHN G4 120 chn 648 equivalent 1/CHN 545
Text: XRT86L38 PRELIMINARY PRELIMINARY OCTAL T1/E1/J1 FRAMER/LIU COMBO MAY 2004 REV. P1.1.1 GENERAL DESCRIPTION The XRT86L38 is an eight-channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated solution featuring R3 technology Relayless, Reconfigurable, Redundancy . The physical interface is optimized with internal impedance, and with the patented pad structure, the XRT86L38 provides protection
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XRT86L38
XRT86L38
TR54016,
G-703,
chn 924
CHN 643
144T1
CHN G4 120
chn 648 equivalent
1/CHN 545
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D4710
Abstract: M01F E853 M6G DATASHEET z421 A616 K4170 5A6Y
Text: E= 70D056='*A616*9F)18*?)G,*H I>G)D/)=*+JJH !"#$%&' )*+,-*./01232*&456/7)8*916/070:);8 <)1=>%?)@0>567*AB?*C62)=*&=652D011)=2 • <Y#BY#$B(P&%$3(5.#(%$ ■ 0%"5'3.##&%4&5"-6&$.5BY# S(70P610>52 ■ F&#%(4%&1.(5"6$5&#P(%:'$#($789$:3 ■ \&%I$2&5'&T$P"Q&42.Q.'.(5$3Y6#.B6&O.51$]!S!F^
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70D056=
652D011)
70P610
D4710
M01F
E853
M6G DATASHEET
z421
A616
K4170
5A6Y
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chn 614
Abstract: D4710 s04999d8e chn 706 z421 A616 Y-625 s 513b
Text: E= 70D056='*A616*9F)18*?)G,*+ H)/=46='*+II+ !"#$%&' )*+,-*./01232*&456/7)8*916/070:);8 <)1=>%?)@0>567*AB?*C62)=*&=652D011)=2 • <Y#BY#$B(P&%$3(5.#(%$ ■ 0%"5'3.##&%4&5"-6&$.5BY# S(70P610>52 ■ F&#%(4%&1.(5"6$5&#P(%:'$#($789$:3 ■ \&%I$2&5'&T$P"Q&42.Q.'.(5$3Y6#.B6&O.51$]!S!F^
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70D056=
652D011)
70P610
D4710
4DG98^
chn 614
s04999d8e
chn 706
z421
A616
Y-625
s 513b
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CHN G4 141
Abstract: No abstract text available
Text: XRT86L38 PRELIMINARY PRELIMINARY OCTAL T1/E1/J1 FRAMER/LIU COMBO APRIL 2004 REV. P1.1.0 GENERAL DESCRIPTION The XRT86L38 is an eight-channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated solution featuring R3 technology Relayless, Reconfigurable, Redundancy . The physical interface is optimized with internal impedance, and with the patented pad structure, the XRT86L38 provides protection
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XRT86L38
XRT86L38
CHN G4 141
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PAIRGAIN
Abstract: CHN 552 Motorola wireless router Type 0X69 BT8953EPF E1 PCM encoder RS8953B RS8953BEPF RS8953BEPJ RS8953SPB Water level indicator using 8051
Text: RS8953B/8953SPB HDSL Channel Unit The RS8953B is a High-Bit-Rate Digital Subscriber Line HDSL channel unit designed to perform data, clock, and format conversions necessary to construct a Pulse Code Multiplexed (PCM) channel from one, two, or three HDSL channels. The PCM channel
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RS8953B/8953SPB
RS8953B
Bt8370
Bt8970
PAIRGAIN
CHN 552
Motorola wireless router Type 0X69
BT8953EPF
E1 PCM encoder
RS8953BEPF
RS8953BEPJ
RS8953SPB
Water level indicator using 8051
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Motorola wireless router Type 0X69
Abstract: "routing tables" bt8953
Text: R O C K W E L L Network access S E M I C O N D U C T O R Bt8953A/SP HDSL Channel Unit data sheet PROVIDING HIGH SPEED MULTIMEDIA CONNECTIONS Because Communication Matters S Y S T E M S Advance Information This document contains information on a product under development. The parametric information contains target
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Bt8953A/SP
Bt8953A/8953SP
Bt8953A
Motorola wireless router Type 0X69
"routing tables"
bt8953
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CHN 712
Abstract: Motorola wireless router Type 0X69 HDSL Modem circuit diagram bt8953 chn 513 "routing tables" CHN 517 Motorola Router Type 0X69
Text: Advance Information This document contains information on a product under development. The parametric information contains target parameters that are subject to change. RS8953B/8953SPB HDSL Channel Unit The RS8953B is a High-Bit-Rate Digital Subscriber Line HDSL channel unit
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RS8953B/8953SPB
RS8953B
Bt8370
CHN 712
Motorola wireless router Type 0X69
HDSL Modem circuit diagram
bt8953
chn 513
"routing tables"
CHN 517
Motorola Router Type 0X69
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chn 850
Abstract: 11-T0 05B2 QL5064-66BPS484C quicklogic 5064 QL5064
Text: 4/ 4XLFN3&, 'DWD 6KHHW W W W W W W 0+]ELW 3&, 0DVWHU7DUJHW ZLWK PEHGGHG 3URJUDPPDEOH /RJLF DQG GXDO 3RUW 65$0 'HYLFH +LJKOLJKWV +LJK 3HUIRUPDQFH 3&, &RQWUROOHU 64-bit / 66 MHz Master/Target PCI Controller (automatically backwards
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64-bit
32-bits)
busses/100
chn 850
11-T0
05B2
QL5064-66BPS484C
quicklogic 5064
QL5064
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CHN G4 309
Abstract: 40 serice free DMO 565 R CHN 932
Text: xr XRT86L38 PRELIMINARY OCTAL T1/E1/J1 FRAMER/LIU COMBO JANUARY 2005 REV. P1.1.7 GENERAL DESCRIPTION The XRT86L38 is an eight-channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated solution featuring R3 technology Relayless, Reconfigurable, Redundancy .
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XRT86L38
XRT86L38
CHN G4 309
40 serice free
DMO 565 R
CHN 932
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ST CHN 510
Abstract: 83C97 chn 809 chn 809 ST
Text: 83C97 T e chn o log y, In co rp o rate d 10BASE-T Ethernet Transceiver With On Chip Filters and Digital Interface and Serial Port PRELIMINARY October 1994 SEEQ AutoDUPLEX Designation S ym bol indentifies product as A u to D U P L E X device. Description
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83C97
10BASE-T
83C97
10BASET)
ST CHN 510
chn 809
chn 809 ST
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Transistor TT 2246
Abstract: transistor chn 911 TT 2246 transistor jm31a pulse electronics era transformer transistor chn 037 chn 809 S4744
Text: SEEQ T e chn o log y, Inco rp o rate d 83C96 10BASE-T Ethernet Transceiver With On Chip Filters and Digital Interface PRELIMINARY October 1994 SEEQ AutoDUPLEX Designation Sym bol indentifies product as A u to D U P L E X device. Description The 83C96 is a highly integrated analog interface 1C for
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83C96
10BASE-T
83C96
10BASET)
10BASET
Transistor TT 2246
transistor chn 911
TT 2246 transistor
jm31a
pulse electronics era transformer
transistor chn 037
chn 809
S4744
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Internal diagram of ic 7495
Abstract: chn 706 chn 807 Framer
Text: Product Brief September 1998 gr oup Lucent Technologies Bell Labs Innovations TFRA08C13 Octal T1/E1 Framer • 3.3 V low-power CMOS with 5 V tolerant inputs. ■ Available in 352-pin PBGA. Features ■ Eight independent T1/E1 transmit and receive framers.
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TFRA08C13
352-pin
Su7070
PN98-192TIC
PN98-126TIC)
Internal diagram of ic 7495
chn 706
chn 807
Framer
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DDMA78P
Abstract: ddma78s chn 605 DD-78
Text: 1 *MA H ig h D ensity D C rim p P r i n t e d C irc u it See page 342) (See page 343) Perfo rm a n ce and M a te ria l S pecific a tio n s M A T E R IA L S A N D F IN IS H E S Standard M ilita ry M aterial Finish M aterial S h e lf S teel pe t A S T M A -6 2 0
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DD-78
CIET-22D
DDMA78P
ddma78s
chn 605
DD-78
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Untitled
Abstract: No abstract text available
Text: 1.0 HDSL Systems 1.1 HTU Applications The High-Bit-Rate Digital Subscriber Line HDSL is a simultaneous full-duplex transmission scheme, which uses twisted-pair wire cables as the physical medium to transport signals between standard types of network or subscriber
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N8953BDSA
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