CI 4835 D Search Results

Ic 7442

Contextual Info: S C IE N TIF IC / M I N I - C I R C U IT S 4RE D • fiO b B B ll 000 13 4 7 f l S l H S C C plug-in, surface-m ount Frequency Mixers Models t-74-°9-01 I CV/CI -7 F-3 TUF-3SM L tV tL / + 7 dBm LO, up to +1 dBm RF computer-automated performance data typical production unit / for data of other models consult factory

AHC1G04

Abstract: SN74AHC1G04H
Contextual Info: SN74AHC1G04 SINGLE INVERTER GATE SCLS318Q − MARCH 1996 − REVISED JUNE 2005 D D D D D Schmitt Trigger Action at All Inputs Makes Operating Range of 2 V to 5.5 V Max tpd of 6.5 ns at 5 V Low Power Consumption, 10-µA Max ICC ±8-mA Output Drive at 5 V D

military radar 20 pages documentation

Abstract: SN74LVTH373-EP
Contextual Info: SN74LVTH373ĆEP 3.3ĆV ABT OCTAL TRANSPARENT DĆTYPE LATCH WITH 3ĆSTATE OUTPUTS SCBS770 − NOVEMBER 2003 D Controlled Baseline D D D D D D D D Bus Hold on Data Inputs Eliminates the − One Assembly/Test Site, One Fabrication Site Enhanced Diminishing Manufacturing

CI 4835 b

Contextual Info: SN74AC32ĆEP QUADRUPLE 2ĆINPUT POSITIVEĆOR GATE SCAS720 − OCTOBER 2003 D Controlled Baseline D D D D D 2-V to 6-V VCC Operation D Inputs Accept Voltages to 6 V D Max tpd of 7.5 ns at 5 V − One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of

cmos testing abstract

Contextual Info: SN74ACT1071 10-BIT BUS-TERMINATION ARRAY WITH BUS-HOLD FUNCTION SCAS192 – D3994, MARCH 1992 – REVISED APRIL 1993 • • • • • • • D PACKAGE TOP VIEW Designed to Ensure Defined Voltage Levels on Floating Bus Lines in CMOS Systems Reduces Undershoot and Overshoot

Contextual Info: SN74BCT757 OCTAL BUFFER/DRIVER WITH OPEN-COLLECTOR OUTPUTS SCBS041D – NOVEMBER 1989 – REVISED NOVEMBER 1993 • • • • DW OR N PACKAGE TOP VIEW BiCMOS Design Significantly Reduces ICCZ ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds

Contextual Info: SN74AC04ĆEP HEX INVERTER SCAS717 − OCTOBER 2003 D Controlled Baseline D D D D − One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of −55°C to 125°C Enhanced Diminishing Manufacturing Sources DMS Support Enhanced Product-Change Notification

Contextual Info: SN74AC08ĆEP QUADRUPLE 2ĆINPUT POSITIVEĆAND GATE SCAS718 − OCTOBER 2003 D Controlled Baseline D D D D D 2-V to 6-V VCC Operation D Inputs Accept Voltages to 6 V D Max tpd of 7.5 ns at 5 V − One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of

newark

Abstract: AHC1G08 TAS5066-5121K6EVM
Contextual Info: SN74AHC1G08 SINGLE 2ĆINPUT POSITIVEĆAND GATE SCLS314M − MARCH 1996 − REVISED JUNE 2005 D D D D D D Latch-Up Performance Exceeds 250 mA Per Operating Range of 2 V to 5.5 V Max tpd of 7 ns at 5 V Low Power Consumption, 10-µA Max ICC ±8-mA Output Drive at 5 V

Contextual Info: [ /Title CD54H C08, CD54H CT08, CD74H C08, CD74H CT08 /Subject (High CD54HC08, CD74HC08, CD54HCT08, CD74HCT08 Data sheet acquired from Harris Semiconductor SCHS118C High-Speed CMOS Logic Quad 2-Input AND Gate August 1997 - Revised July 2004 Features Description

74hc30

Contextual Info: [ /Title CD54H C30, CD74H C30, CD74H CT30 /Subject (High Speed CMOS Logic 8- CD54/74HC30, CD54/74HCT30 Data sheet acquired from Harris Semiconductor SCHS121D High Speed CMOS Logic 8-Input NAND Gate August 1997 - Revised September 2003 Features Description

Contextual Info: SN74HSTL162822 14-BIT TO 28-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH SCES091A – DECEMBER 1996 – REVISED APRIL 1997 D D D D DGG PACKAGE TOP VIEW Member of the Texas Instruments Widebus Family Inputs Meet JEDEC HSTL Standard JESD8-6 All Outputs Have Equivalent 25-Ω Series

Contextual Info: SN74HSTL16918 9-BIT TO 18-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH SCES096C – APRIL 1997 – REVISED JANUARY 1999 D D D D D DGG PACKAGE TOP VIEW Member of the Texas Instruments Widebus Family Inputs Meet JEDEC HSTL Std JESD 8-6 and Outputs Meet Level III Specifications

nom 8370 b

Contextual Info: 74AC11000 QUADRUPLE 2-INPUT POSITIVE-NAND GATE www.ti.com SCLS054B – APRIL 1987 – REVISED JUNE 2005 FEATURES • • • • D OR N PACKAGE TOP VIEW Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPIC (Enhanced-Performance Implanted

Contextual Info: SN74HC02ĆEP QUADRUPLE 2ĆINPUT POSITIVEĆNOR GATE SCLS478A − APRIL 2003 − REVISED JANUARY 2004 D Controlled Baseline D D D D D D D D D D − One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of Up To −55°C to 125°C Enhanced Diminishing Manufacturing

Contextual Info: SN74HSTL16919 9-BIT TO 18-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH WITH INPUT PULLUP RESISTORS SCES348 – MARCH 2001 D D D D D DGG PACKAGE TOP VIEW Member of Texas Instruments’ Widebus Family Inputs Meet JEDEC HSTL Std JESD 8-6, and Outputs Meet Level III Specifications

Contextual Info: SN74S1051 12-BIT SCHOTTKY BARRIER DIODE BUS-TERMINATION ARRAY SDLS018B – SEPTEMBER 1990 – REVISED MARCH 2003 D D D D, N, NS, OR PW PACKAGE TOP VIEW Designed to Reduce Reflection Noise Repetitive Peak Forward Current to 200 mA 12-Bit Array Structure Suited for

Contextual Info: SN74AHCT1G32ĆQ1 SINGLE 2ĆINPUT POSITIVEĆOR GATE SCLS606A − MARCH 2005 − MARCH 2005 D Qualification in Accordance With DBV OR DCK PACKAGE TOP VIEW AEC-Q100† D Qualified for Automotive Applications D Customer-Specific Configuration Control D D D D

Contextual Info: [ /Title CD74 HC86, CD74 HCT86 /Subject (High Speed CMOS Logic Quad 2-Input EXCL USIVE OR CD54HC86, CD74HC86, CD54HCT86, CD74HCT86 Data sheet acquired from Harris Semiconductor SCHS137D High-Speed CMOS Logic Quad 2-Input EXCLUSIVE-OR Gate August 1997 - Revised September 2003

Contextual Info: SN74S1051 12-BIT SCHOTTKY BARRIER DIODE BUS-TERMINATION ARRAY SDLS018B – SEPTEMBER 1990 – REVISED MARCH 2003 D D D D, N, NS, OR PW PACKAGE TOP VIEW Designed to Reduce Reflection Noise Repetitive Peak Forward Current to 200 mA 12-Bit Array Structure Suited for

Contextual Info: SN64BCT125A QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS SCBS052B – JULY 1990 – REVISED MAY 1994 • • • • • D OR N PACKAGE TOP VIEW State-of-the-Art BiCMOS Design Significantly Reduces ICCZ High-Impedance State During Power-Up and Power-Down

Contextual Info: SN74ACT1073 16-BIT BUS-TERMINATION ARRAY WITH BUS-HOLD FUNCTION SCAS193A – MARCH 1992 – REVISED NOVEMBER 2002 D D D D D D D D D DW OR NS PACKAGE TOP VIEW Designed to Ensure Defined Voltage Levels on Floating Bus Lines in CMOS Systems 4.5-V to 5.5-V VCC Operation

Contextual Info: SN74SSTL16847 20-BIT SSTL_3 INTERFACE BUFFER WITH 3-STATE OUTPUTS SCBS709A – OCTOBER 1997 – REVISED MAY 1998 D D D D D D D DGG PACKAGE TOP VIEW Member of the Texas Instruments Widebus Family Supports SSTL_3 Signal Inputs and Outputs Flow-Through Architecture Optimizes PCB

transistor data book free

Abstract: transistor data book free download CI 4835 b Cross ReferenceTransistor Book all transistor data sheet book download
Contextual Info: SN74TVC3306 DUAL VOLTAGE CLAMP www.ti.com SCDS112C – MARCH 2001 – REVISED MARCH 2005 FEATURES • DCT OR DCU PACKAGE TOP VIEW Designed to Be Used in Voltage-Limiting Applications 3.5-Ω On-State Connection Between Ports A and B Flow-Through Pinout for Ease of Printed