CI T314 Search Results

STG60

Abstract: OPTREX DMC 93IC DMC-60S DMC-50593NFJ-SLY-2
Contextual Info: OVIj rot LCD M odule S p e c ific a tio n ^ C h e c X ir i ty O’tS y rt Pftpen'd b]r Typut NO, *•' tn g ln e c rfp g U fV . pTOdU<!.;Qff 0 « . PM C -5 0 5 9 3 N F J - S L Y - 2 EA ble o f C o n t e n ts I. G e n e ra ! ] . S p tf tific a iio fis

ST*10f269-q3

Abstract: syscon sw 301 st10 Bootstrap ST10F269-T3 dp3121
Contextual Info: ST10F269-T3 16-BIT MCU WITH MAC UNIT, 256K BYTE FLASH MEMORY AND 12K BYTE RAM March 2003 FAIL-SAFE PROTECTION – PROGRAMMABLE WATCHDOG TIMER – OSCILLATOR WATCHDOG • ■ ON-CHIP BOOTSTRAP LOADER CLOCK GENERATION – ON-CHIP PLL – DIRECT OR PRESCALED CLOCK INPUT

ST10F269-Q3

Abstract: GPR circuit schematic diagram full data shed diode BA 159 free ST*10f269-q3 PQFP144 ST10F269 E-ST10F269 st10 Bootstrap ST10F269 03
Contextual Info: ST10F269 16-BIT MCU WITH MAC UNIT, 256K BYTE FLASH MEMORY AND 12K BYTE RAM PRELIMINARY DATA • ■ ■ ■ 16 32 256K Byte FlashMemory 2K Byte Internal RAM 16 CPU-Core andMACUnit Watchdog 16 PEC 10KByte XRAM 16 16 8 16 Interrupt Controller XTAL1 3.3V Port6

st10 Bootstrap

Abstract: ST10F269Q
Contextual Info: ST10F269Z2Qx 16-BIT MCU WITH MAC UNIT, 256K BYTE FLASH MEMORY AND 12K BYTE RAM PRELIMINARY DATA August 2002 • ■ IDLE AND POWER DOWN MODES SINGLE VOLTAGE SUPPLY: 5V ±10% EMBEDD ED REGULATOR FOR 3.3 V CORE SUPPLY . TEMPERATURE RANGES: -40 +125°C, -40 to 85°C

GPR circuit schematic diagram full

Abstract: DP43 T308 ST10F269-T6 ST*10f269-q3 m29F ST10F269-T3 TQFP144 f082h st10 Bootstrap
Contextual Info: ST10F269-T3 16-BIT MCU WITH MAC UNIT, 256K BYTE FLASH MEMORY AND 12K BYTE RAM March 2003 FAIL-SAFE PROTECTION – PROGRAMMABLE WATCHDOG TIMER – OSCILLATOR WATCHDOG • ■ ON-CHIP BOOTSTRAP LOADER CLOCK GENERATION – ON-CHIP PLL – DIRECT OR PRESCALED CLOCK INPUT

GPR circuit schematic diagram full

Abstract: ST10F269Z2q3 PQFP144 ST10 ST10F269 03 T48 regulator st10 Bootstrap
Contextual Info: ST10F269Z2Qx 16-BIT MCU WITH MAC UNIT, 256K BYTE FLASH MEMORY AND 12K BYTE RAM PRELIMINARY DATA August 2002 • ■ 16 32 256K Byte Flash Memory 2K Byte Internal RAM 16 CPU-Core and MAC Unit Watchdog 16 10K Byte XRAM PEC Oscillator and PLL CAN1_RXD CAN1_TXD

GPR circuit schematic diagram full

Abstract: ST10F269-Q3 ST10F169 PQFP144 DCMI timing specification st10 Bootstrap gpr schematic diagram EA99
Contextual Info: ST10F269-Q3 16-BIT MCU WITH 256K BYTE FLASH MEMORY AND 12K BYTE RAM PRELIMINARY DATA • ■ ■ ■ 16 32 256KByte FlashMemory 2K Byte Internal RAM 16 CPU-Coreand MACUnit Watchdog 16 10KByte XRAM PEC 16 16 8 16 Interrupt Controller XTAL1 Port 6 8 Port5 16

ST10F269 03

Abstract: GPR circuit schematic diagram full PQFP144 ST10F269 ST10F269-Q3 st10 Bootstrap FE90
Contextual Info: ST10F269 16-BIT MCU WITH MAC UNIT, 256K BYTE FLASH MEMORY AND 12K BYTE RAM PRELIMINARY DATA • ■ ■ ■ 16 32 256K Byte Flash Memory 2K Byte Internal RAM 16 CPU-Core and MAC Unit Watchdog 16 10K Byte XRAM PEC Oscillator and PLL CAN1_RXD CAN1_TXD CAN1 CAN2_RXD

Contextual Info: ST10F269 16-BIT MCU WITH MAC UNIT, 256K BYTE FLASH MEMORY AND 12K BYTE RAM PRELIMINARY DATA September 2013 • ■ ■ ■ 16 32 256K Byte Flash Memory 2K Byte Internal RAM 16 CPU-Core and MAC Unit Watchdog 16 10K Byte XRAM PEC Oscillator and PLL CAN1_RXD

Contextual Info: ST10F269-T3 16-BIT MCU WITH MAC UNIT, 256 KBYTE FLASH MEMORY AND 12 KBYTE RAM September 2013 Rev 3 – PROGRAMMABLE WATCHDOG TIMER – OSCILLATOR WATCHDOG • ■ ON-CHIP BOOTSTRAP LOADER CLOCK GENERATION – ON-CHIP PLL – DIRECT OR PRESCALED CLOCK INPUT

ST10F269-T3

Abstract: ST10F269-T6 CAN BUS GPR circuit schematic diagram full st10f269t3 ST*10f269-q3 LQFP144 P0151 st10 Bootstrap 5P35
Contextual Info: ST10F269-T3 16-BIT MCU WITH MAC UNIT, 256 KBYTE FLASH MEMORY AND 12 KBYTE RAM January 2009 Rev 2 – PROGRAMMABLE WATCHDOG TIMER – OSCILLATOR WATCHDOG • ■ ON-CHIP BOOTSTRAP LOADER CLOCK GENERATION – ON-CHIP PLL – DIRECT OR PRESCALED CLOCK INPUT ■

st10 Bootstrap

Abstract: ST10f269 ST10F269-DPR ST10F269 03
Contextual Info: ST10F269 16-BIT MCU WITH MAC UNIT, 256K BYTE FLASH MEMORY AND 12K BYTE RAM PRELIMINARY DATA • ■ ■ ■ 16 32 256K Byte Flash Memory 2K Byte Internal RAM 16 CPU-Core and MAC Unit Watchdog 16 10K Byte XRAM PEC Oscillator and PLL CAN1_RXD CAN1_TXD CAN1 CAN2_RXD

Contextual Info: ST10F269 16-BIT MCU WITH MAC UNIT, 256K BYTE FLASH MEMORY AND 12K BYTE RAM PRELIMINARY DATA • ■ ■ ■ 16 32 256K Byte Flash Memory 2K Byte Internal RAM 16 CPU-Core and MAC Unit Watchdog 16 10K Byte XRAM PEC Oscillator and PLL CAN1_RXD CAN1_TXD CAN1 CAN2_RXD

error multiplexer parity comparator

Abstract: PQFP144 ST10 ST10F269 TQFP144 1221h ST10F269 03 st10 Bootstrap p46a
Contextual Info: ST10F269Zx 16-BIT MCU WITH MAC UNIT, 128K to 256K BYTE FLASH MEMORY AND 12K BYTE RAM DATASHEET • ■ 128K or 256KByte Flash Memory 2K Byte Internal RAM 16 CPU-Core and MAC Unit Watchdog 16 10K Byte XRAM 16 16 8 16 Interrupt Controller 8 Por t 5 16 BRG BRG

st10 Bootstrap

Abstract: T03-15 ST10F269 03
Contextual Info: ST10F269 16-BIT MCU WITH MAC UNIT, 128K to 256K BYTE FLASH MEMORY AND 12K BYTE RAM DATASHEET • ■ 2K Byte Internal RAM 16 CPU-Core and MAC Unit Watchdog 16 10K Byte XRAM CAN1_RXD CAN1_TXD CAN1 CAN2_RXD CAN2_TXD CAN2 PEC Oscillator and PLL 16 Interrupt Controller

Contextual Info: ST10F269Zx 16-BIT MCU WITH MAC UNIT, 128K to 256K BYTE FLASH MEMORY AND 12K BYTE RAM DATASHEET • ■ 128K or 256KByte Flash Memory 2K Byte Internal RAM 16 CPU-Core and MAC Unit Watchdog 16 10K Byte XRAM 16 16 8 16 Interrupt Controller 8 Por t 5 16 BRG BRG

C100H

Abstract: PIN DIAGRAM of st10f280 EE30h st10 Bootstrap BUT16
Contextual Info: ST10F280 16-BIT MCU WITH MAC UNIT, 512K BYTE FLASH MEMORY AND 18K BYTE RAM PRODUCT PREVIEW • ON-CHIP BOOTSTRAP LOADER CLOCK GENERATION - ON-CHIP PLL. - DIRECT OR PRESCALED CLOCK INPUT. ■ UP TO 143 GENERAL PURPOSE I/O LINES - INDIVIDUALLY PROGRAMMABLE AS INPUT, OUTPUT OR SPECIAL FUNCTION.

XP91

Abstract: JH17 ST10F280 ST10F280-JT3 st10 Bootstrap f08e BUT16
Contextual Info: ST10F280 16-BIT MCU WITH MAC UNIT, 512K BYTE FLASH MEMORY AND 18K BYTE RAM PRODUCT PREVIEW • ON-CHIP BOOTSTRAP LOADER CLOCK GENERATION - ON-CHIP PLL. - DIRECT OR PRESCALED CLOCK INPUT. ■ UP TO 143 GENERAL PURPOSE I/O LINES - INDIVIDUALLY PROGRAMMABLE AS INPUT, OUTPUT OR SPECIAL FUNCTION.

PIN DIAGRAM of st10f280

Abstract: CONNEXION ST10F280-JT3 XP1010 XP95 F194 ST10F280 p21015 g4 pc 50 w XP91
Contextual Info: ST10F280 16-BIT MCU WITH MAC UNIT, 512K BYTE FLASH MEMORY AND 18K BYTE RAM PRODUCT PREVIEW • ON-CHIP BOOTSTRAP LOADER CLOCK GENERATION - ON-CHIP PLL. - DIRECT OR PRESCALED CLOCK INPUT. ■ UP TO 143 GENERAL PURPOSE I/O LINES - INDIVIDUALLY PROGRAMMABLE AS INPUT, OUTPUT OR SPECIAL FUNCTION.

Contextual Info: ST10F280 16-bit MCU with MAC unit, 512 Kbyte Flash memory and 18 Kbyte RAM Datasheet − production data Features • ■ ■ ■ High performance cpu with dsp functions – 16-bit CPU with 4-stage pipeline. – 50ns Instruction cycle time at 40MHz CPU clock

PIN DIAGRAM of st10f280

Abstract: ST10F280 ST10F280-JT3 g4 pc 50 w st10 Bootstrap ptix BUT16 EE00h
Contextual Info: ST10F280 16-BIT MCU WITH MAC UNIT, 512K BYTE FLASH MEMORY AND 18K BYTE RAM PRODUCT PREVIEW • ON-CHIP BOOTSTRAP LOADER CLOCK GENERATION - ON-CHIP PLL. - DIRECT OR PRESCALED CLOCK INPUT. ■ UP TO 143 GENERAL PURPOSE I/O LINES - INDIVIDUALLY PROGRAMMABLE AS INPUT, OUTPUT OR SPECIAL FUNCTION.

Contextual Info: ST10F280 16-bit MCU with MAC unit, 512 Kbyte Flash memory and 18 Kbyte RAM Datasheet − production data Features • ■ ■ ■ High performance cpu with dsp functions – 16-bit CPU with 4-stage pipeline. – 50ns Instruction cycle time at 40MHz CPU clock

PIN DIAGRAM of st10f280

Abstract: DC2D4 st10 Bootstrap BUT16
Contextual Info: ST10F280 16-bit MCU with MAC unit, 512 Kbyte Flash memory and 18 Kbyte RAM Datasheet − production data Features • ■ ■ ■ High performance cpu with dsp functions – 16-bit CPU with 4-stage pipeline. – 50ns Instruction cycle time at 40MHz CPU clock

motorola t217

Abstract: ATM25 C10535E T322 making RDIP
Contextual Info: DATA SHEET MOS INTEGRATED CIRCUIT µPD98408 6-PORT 25M ATM PHY LSI The µPD98408 is an ATM physical layer LSI IC that complies with ATM25 25.6 Mbps and which supports TC sublayer and PMD sublayer functions. Interfacing with the ATM layer and AAL layer LSI is implemented at UTOPIA