CIBL723 Search Results

SN54ALS646

Abstract: SN54ALS648 SN54AS646 SN74AS646 SN74AS648 SN74ALS646-1
Contextual Info: SN74ALS646, SN74ALS648. SN74AS646, SN74AS648 SN54ALS646, SN54ALS648, SN54AS646 OCTAL BUS TRANSCEIVERS AND REGISTERS D 26 61 , D E C E M B E R 1 9 8 3 - R EV IS E D O C T O B E R 1991 Independent Registers for A and B Buses SN34ALS . S N 54A S ' JT PACKAGE

Contextual Info: SN74ALS994 10-BIT D-TYPE TRANSPARENT READ-BACK LATCH SDAS237A - OCTOBER 1984 - REVISED JANUARY 1995 • • • • 3-State l/O-Type Read-Back Inputs Bus-Structured Pinout True Logic Outputs Package Options Include Plastic Small-Outline DW Packages and Standard

SN54ABT16657

Abstract: SN74ABT16657 1561T
Contextual Info: SN54ABT16657, SN74ABT16657 16-BIT TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS AND 3-STATE OUTPUTS SCBS103A-FEBRUARY 1992-REVISED JULY 1994 Members of the Texas Instruments IV/debus Family State-of-the-Art fP/C-IIB™ BiCMOS Design Significantly Reduces Power Dissipation

SB3B

Abstract: SN54ABT32245 SN74ABT32245
Contextual Info: SN54ABT32245, SN74ABT32245 36-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS S C B S 2 2 8 B -J U N E 1 9 9 2 - REVISED JULY 1994 Distributed Vcc and GND Pin Configuration Minimizes High-Speed Switching Noise High-Drive Outputs -32-mA Ioh . 64-mA Io l Bus-Hold Inputs Eliminate the Need for

SN54AHC74

Abstract: SN74AHC74
Contextual Info: SN54AHC74, SN74AHC74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET _ SC LS 255B - DECEMBER 1 9 9 5 - REVISED JULY 1996 Operating Range 2-V to 5.5-V Vc c S N 5 4 A H C 7 4 . . . J OR W PACKAGE SN74AHC 74 . . . D, DB, N, OR PW PACKAGE