CLK 502 Search Results

93LC46

Abstract: 93LC46C 93LC56 93LC56C 93LC66 93LC66C 9786
Contextual Info: Not recommended for new designs – Please use 93LC46C, 93LC56C or 93LC66C. 93LC46/56/66 1K/2K/4K 2.5V Microwire Serial EEPROM Features: Package Types CS CLK 1 2 DI DO 3 8 7 VCC NU 6 4 5 ORG VSS NU VCC 1 2 8 7 ORG VSS CS CLK 3 6 DO DI ROTATED SOIC 93LC46X

SN0410

Abstract: 93LC76 93C76 93C86 93LC76C 93LC86C MS-001
Contextual Info: Not recommended for new designs – Please use 93LC76C or 93LC86C. 93C76/86 8K/16K 5.0V Microwire Serial EEPROM Features: PDIP Package CS 1 CLK DI DO 2 3 4 93C76/86 8 VCC 7 6 5 PE ORG VSS SOIC Package CS CLK DI DO 1 2 3 4 93C76/86 • Single 5.0V supply • Low-power CMOS technology

37LV128

Abstract: 37LV36 37LV65 XC1700
Contextual Info: Obsolete Device 37LV36/65/128 36K, 64K, and 128K Serial EPROM Family FEATURES 8 VCC 7 VPP 6 CEO 4 5 VSS DATA 1 8 VCC CLK 2 7 VPP RESET/OE 3 6 CEO CE 4 5 VSS DATA 1 CLK 2 RESET/OE 3 CE SOIC 37LV36 37LV65 37LV128 PLCC Bits Programming Word 37LV36 36,288 1134 x 32

Contextual Info: Obsolete Device 37LV36/65/128 36K, 64K, and 128K Serial EPROM Family FEATURES DATA 1 CLK 2 RESET/OE 3 CE 8 VCC 7 VPP 6 CEO 4 5 VSS DATA 1 8 VCC CLK 2 7 VPP RESET/OE 3 6 CEO CE 4 5 VSS SOIC 37LV36 37LV65 37LV128 PLCC Bits Programming Word 37LV36 36,288 1134 x 32

93AA66

Abstract: 93AA46 93AA46C 93AA56 93AA56C 93AA66C 56XT
Contextual Info: Not recommended for new designs – Please use 93AA46C, 93AA56C or 93AA66C. 93AA46/56/66 1K/2K/4K 1.8V Microwire Serial EEPROM Features: Package Types +70°C -40°C to +85°C 1 8 V CC CLK 2 7 NU DI 3 6 ORG DO 4 5 V SS CS 1 8 V CC CLK 2 7 NU DI 3 6 ORG DO 4

DSX221S

Abstract: SiW3500 bluetooth Coexistence 3-wire OEN 46 1458 CLK32 l8838 bluetooth transmitter receiver parallel chip mobile
Contextual Info: SiW3500 Preliminary • Bluetooth specification V1.2 qualified including mandatory and optional functions such as AFH and eSCO. PLL Control ADDRESS BUS VDD_P VBB_OUT VCC_OUT VBATT_DIG VBATT_ANA XTAL_N CLK_REQ_IN XTAL_P/CLK CLK_REQ_OUT VTUNE • RF System on Chip SoC for

CQFP 240

Abstract: 8Kx32 ADSP-21060 16Kx32 ADSP21060 AD14060
Contextual Info: DIGITAL SIGNAL PROCESSING: FLOATING POINT MODEL MODEL MFLOPS MIPS CYLCE TIME nsec CLK IN MHZ PROGRAM RAM ROM DATA RAM CACHE SERIAL PORTS HOST PORT SISD Single Instruction Single Data NO NO NO NO +3.3V NO NO NO NO 64Kx32 64Kx32 64Kx32 64Kx32 64Kx32 64Kx32

Contextual Info: HD74ALVCH16820 Preliminary 3.3-V 10-bit Flip Flops with Dual Outputs Description The flip flops of the HD74ALVCH16820 are edge triggered D-type flip flops. On the positive transition of the clock CLK input, the device provides true data at the Q outputs. A buffered output enable (OE) input

Contextual Info: CDCV857B, CDCV857BI 2.5-V PHASE-LOCK LOOP CLOCK DRIVER SCAS689 – FEBRUARY 2003 D Phase-Lock Loop Clock Driver for Double D D D D D D D Enters Low-Power Mode When No CLK Data-Rate Synchronous DRAM Applications Spread Spectrum Clock Compatible Operating Frequency: 60 MHz to 200 MHz

CPU 6502

Abstract: K133 6502 CPU RESONATOR 4MHZ 6502C type pd21 009F NT6868C NT6868CH K131
Contextual Info: NT6868C Keyboard Controller Features n n n n n n Mask optional for built-in RC oscillator with an external resistor or external ceramic resonator applied n Mask optional for DATA/CLK driving capability n Watch-dog timer n Built-in power-on reset n Built-in low voltage reset

93AA76

Abstract: 93AA76C 93AA86 93AA86C MS-001 SN0410
Contextual Info: Not recommended for new designs – Please use 93AA76C or 93AA86C. 93AA76/86 8K/16K 1.8V Microwire Serial EEPROM Features: PDIP Package 1 CLK DI DO 2 3 4 8 VCC 7 6 5 PE ORG 93AA76/86 CS 93AA76/86 • Single supply operation down to 1.8V • Low-power CMOS technology:

Contextual Info: 16M SDRAM TIMING LG Semicon Timing Waveforms BankO Active BankO Préchargé BankO Read B urst length = 4 BankO A ccess H i = V ih o r V», 495 16M SDRAM TIMING L6 Semicon Timing Waveforms Write Cycle tCK KM tc k l •* in t' CLK tKC CKE V ih* tRP tRAS ÎRCD

F5401

Abstract: io 1207 100MHZ 54-PIN F5402
Contextual Info: PRELIMINARY SPACE ELECTRONICS INC. 1 GIGABIT SYNCHRONOUS DRAM SPACE PRODUCTS VDD 1 97SD10004RP 54 VSS CS 7 NC VDDQ VSSQ CS 6 NC DQ0 DQ3 VSSQ VDDQ CS 5 NC CS 4 NC VDDQ VSSQ CS 3 NC DQ1 DQ2 VSSQ VDDQ CS 2 VDD VSS CS 1 NC/RFU WE DQM NC/A13 CAS CLK RAS CKE CS 0

maa 502

Abstract: VT82C596B VT82C693 SUPER-7
Contextual Info: JEDEC PC133 Unbuffered DIMM Timing Margin Review March 3, 1999 Min a n d m a x lo a d s o f DRAM s ig n a ls • • • • • • CS CLK SRAS,SCAS,SWE,MA MD/DQM CKE Max 5 Loads 5 Loads 36 Loads 8 Loads 9 Loads Min 2 Loads 2 Loads 4 Loads 1 Load 4 Load DRAM Re a d Cycle s : DQs

3200DX

Abstract: FCTD16C TA191 CNT4A AO11 TA273 dece2x4
Contextual Info: Macro Library Guide 1995 This document was created with FrameMaker 4.0.2 Actel Corporation, Sunnyvale, CA 94086  1995 Actel Corporation. All rights reserved. Part Number: 5029009-0 September 1995 No part of this document may be copied or reproduced in any form or by any means

Contextual Info: Cell & Macro Library Guide Actel Corporation, Sunnyvale, CA 94086 2001 Actel Corporation. All rights reserved. Part Number: 5029128-0 Release: February 2001 No part of this document may be copied or reproduced in any form or by any means without prior written consent of Actel.

vhdl code for 8-bit signed adder

Abstract: 5 to 32 decoder using 38 decoder vhdl code one hot state machine
Contextual Info: Actel HDL Coding Style Guide Actel HDL Coding Style Guide Actel Corporation, Sunnyvale, CA 94086 1997 Actel Corporation. All rights reserved. Printed in the United States of America Part Number: 5029105-0 Release: November 1997 No part of this document may be copied or reproduced in any form or by any

8086 vhdl

Abstract: structural vhdl code for multiplexers vhdl coding R3216 3 to 8 line decoder vhdl IEEE format vhdl code 2 to 4 line decoder vhdl IEEE format verilog code 12 bit one hot state machine 8 bit carry select adder verilog code
Contextual Info: Actel HDL Coding Style Guide Actel Corporation, Mountain View, CA 94043 2009 Actel Corporation. All rights reserved. Printed in the United States of America Part Number: 5029105-8 Release: July 2009 No part of this document may be copied or reproduced in any form or by any means without prior written

Contextual Info: Actel HDL Coding Style Guide Windows ® and Unix ® Environments Actel Corporation, Sunnyvale, CA 94086 2001 Actel Corporation. All rights reserved. Printed in the United States of America Part Number: 5029105-6 Release: June 2002 No part of this document may be copied or reproduced in any form or by any

HP700

Abstract: 1N201 SIGNAL PATH designer
Contextual Info: Synopsys VSS Simulation Guide for the SunTM and HP700TM Environment Actel Corporation, Sunnyvale, CA 94086 1995 Actel Corporation. All rights reserved. Printed in the United States of America Part Number: 5029077-0 Release: October 1995 No part of this document may be copied or reproduced in any form or by any

Contextual Info: USH5022 HIGH VOLTAGE 8-CHANNEL ANALOG SWITCH Universa! Semiconductor FEATURES GENERAL DESCRIPTION Full D ielectric Isolation fo r High Reliability 6 0 dB typ ica l O u tp u t O ff Isolation at 10 Mhz The U SH 5022 is an 8-channel high voltage analog s w itc h

HP700

Abstract: verilog code for 8 bit carry look ahead adder carry save adder verilog program catalogue book
Contextual Info: Synopsys Synthesis tm Methodology Guide for the UnixTM Workstations Environments Actel Corporation, Sunnyvale, CA 94086 1995 Actel Corporation. All rights reserved. Printed in the United States of America Part Number: 5029076-0 Release: October 1995 No part of this document may be copied or reproduced in any form or by any

verilog code of 8 bit comparator

Abstract: verilog code of 16 bit comparator verilog code of 2 bit comparator verilog code for timer HP700 verilog code finite state machine uPD 1719 G
Contextual Info: Verilog Simulation Guide for the PC WindowsTM and UnixTM Workstation Environments Actel Corporation, Sunnyvale, CA 94086 1995Actel Corporation. All rights reserved. Printed in the United States of America Part Number: 5029078-0 Release: October 1995 No part of this document may be copied or reproduced in any form or by any

vhdl code for a updown counter for FPGA

Abstract: vhdl led palasm palasm user vhdl code for traffic light control HP700 PAL16R4 traffic light using VHDL vhdl code for full subtractor using logic equations vhdl code for counter value to display on multiplexed seven segment
Contextual Info: ACTmap VHDL Synthesis Methodology Guide Windows & UNIX® Environments Actel Corporation, Sunnyvale, CA 94086 1996 Actel Corporation. All rights reserved. Printed in the United States of America Part Number: 5029002-0 Release: June 1996 No part of this document may be copied or reproduced in any form or by any