CONNECTION FOR 74LS138 Search Results

neural network

Abstract: application of feed back amplifier block diagram of 74LS138 3 to 8 decoder block diagram for neural network connection diagram of ic 74ls138 74LS138 decoder neural network chips
Contextual Info: > NEURAL NETWORK ANALOG CMOS CIRCUITS DENDROST“-1 FEED-FORWARD/FEED-BACK CONNECTION CIRCUIT ARRAY Features: • Performs the equivalent of 4.3 MFLOPS using analog computation • Designed for competitive-type, non-supervised, multi-layer networks • Incorporates sleep-refreshed memory retention mechanism

74LS138PC

Contextual Info: 138 CONNECTION DIAGRAM PINOUT A & 54S/74S138 54LS/74LS138 bi f rC 1-0F-8 DECODER/DEMULTIPLEXER D E S C R IP TIO N — The '138 is a high speed 1-of-8 decoder/dem ultiplexer. This device is ideally suited for high speed bipolar memory chip select ad­ dress decoding. The m ultiple input enables allow parallel expansion to a

74LS138

Abstract: 74LS138 3 to 8 decoder Pin 74LS138 pin diagram ls138 74LS138 3 to 8 decoder notes pin for 74LS138 TTL 74ls138 Truth table of 1 to 16 demultiplexer of 74LS138 3 to 8 decoder 74ls138 truth table
Contextual Info: SN54/74LS138 1-OF-8 DECODER/ DEMULTIPLEXER The LSTTL / MSI SN54 / 74LS138 is a high speed 1-of-8 Decoder / Demultiplexer. This device is ideally suited for high speed bipolar memory chip select address decoding. The multiple input enables allow parallel expansion to a 1-of-24 decoder using just three LS138 devices or to a 1-of-32

74ls138 truth table

Abstract: 74LS138 74 LS 138 DECODER connection for 74LS138 74LS138 3 to 8 decoder Pin demultiplexer 3 to 8 truth table 74ls138 demultiplexer LS138 LOGIC OF 74LS138 of 74LS138 3 to 8 decoder
Contextual Info: g MOTOROLA SN54/74LS138 1-0F-8 DECODER/ DEMULTIPLEXER The LSTTL/MSI SN54/74LS138 is a high speed 1-of-8 Decoder/ Demultiplexer. This device is ideally suited for high speed bipolar memory chip select address decoding. The multiple input enables allow parallel ex­

74LS138 3 to 8 decoder notes

Abstract: 74LS138 DATASHEET motorola 74ls138 TTL 74ls138 FUNCTIONAL APPLICATION OF 74LS138 74LS138 data sheet 74LS138 1 to 8 decoder notes 74LS138 application note 74ls138 LS138 Motorola
Contextual Info: SN54/74LS138 1-OF-8 DECODER/ DEMULTIPLEXER The LSTTL / MSI SN54 / 74LS138 is a high speed 1-of-8 Decoder / Demultiplexer. This device is ideally suited for high speed bipolar memory chip select address decoding. The multiple input enables allow parallel expansion to a 1-of-24 decoder using just three LS138 devices or to a 1-of-32

Contextual Info: January 1988 MM54HCT138/MM74HCT138 3-to-8 Line Decoder General Description the 54LS138/74LS138. All inputs are protected from dam­ age due to static discharge by diodes to Vcc and ground. MM54HCT/MM74HCT devices are intended to interface be­ tween TTL and NMOS components and standard CMOS

block diagram of 74LS138 3 to 8 decoder

Abstract: 74LS138 3 to 8 decoder notes block diagram of 74LS138 1 line to 16 line MM74HCT138N mm54hct138/mm74hct138 54LS138 74HCT 74LS138 C1995 MM54HCT138
Contextual Info: MM54HCT138 MM74HCT138 3-to-8 Line Decoder General Description the 54LS138 74LS138 All inputs are protected from damage due to static discharge by diodes to VCC and ground MM54HCT MM74HCT devices are intended to interface between TTL and NMOS components and standard CMOS

LS139

Abstract: LS138 LS138-LS139 74LS139 DM74LS139N
Contextual Info: LS138-LS139 National Semiconductor 54 LS138/DM 54LS138/DM 74LS138, 54 LS139/DM 54LS139/DM 74LS139 Decoders/Demultiplexers General Description These Schottky-clamped circuits are designed to be used in high-performance memory-decoding or data-routing appli­

Contextual Info: s e m i c o n d u c t o r Revised February 1999 MM74HCT138 3-to-8 Line Decoder the 74LS138. All inputs are protected from damage due to static discharge by diodes to Vc c and ground. General Description The MM74HCT138 decoder utilizes advanced silicon-gate

Ic 74hc138 logic diagram

Contextual Info: Revised February 1999 S E M IC Q N D U C T O R T M MM74HC138 3-to-8 Line Decoder The decoder’s outputs can drive 10 low power Schottky TTL equivalent loads, and are functionally and pin equiva­ lent to the 74LS138. All inputs are protected from damage due to static discharge by diodes to V qq and ground.

74HCT138N

Contextual Info: A I R C H I L D Revised February 1999 S E M I C D N D U C T D R tm MM74HCT138 3-to-8 Line Decoder General Description the 74LS138. All inputs are protected from dam age due to static discharge by diodes to V c c and ground. The M M 74H C T138 deco d e r utilizes advanced silicon-gate

a1275

Contextual Info: MP7610 .the analog plus company TM Octal 14-Bit DAC ArrayTM D/A Converter with Output Amplifier and Serial Data/Address µP Control Logic FEATURES APPLICATIONS • • • • • • • • • • • • • • • • • Eight Independent 14-Bit DACs with Output Amplifiers

ic 74ls138 pdf datasheet

Abstract: 74LS138 DATASHEET MP7610AS MP7610BP MP7610BS MP7610CP MP7610CS MP7611 HP5082-2835 MP7610
Contextual Info: MP7610 Octal 14-Bit DAC ArrayTM D/A Converter with Output Amplifier and Serial Data/Address mP Control Logic June 1998-3 FEATURES • · · · · · · · · · APPLICATIONS Eight Independent 14-Bit DACs with Output Amplifiers Low Power 320 mW typ. Serial Digital Data and Address Port (3-Wire Standard)

pin diagram of ic 74ls138

Abstract: FUNCTIONAL APPLICATION OF 74LS138 connection diagram of ic 74ls138 IC 74ls138 block diagram of 74LS138 3 to 8 decoder 74LS138 3 to 8 decoder notes 74LS138 HP5082-2835 MP7612 MP7612AP
Contextual Info: MP7612 Octal 12-Bit DAC ArrayTM D/A Converter with Output Amplifier and Serial Data/Address µP Control Logic .the analog plus company TM FEATURES APPLICATIONS • Eight Independent 12-Bit DACs with Output Amplifiers • Low Power 320 mW typ. • Serial Digital Data and Address Port (3-Wire

DM74367

Abstract: 54175 71ls97 DM74109 DM8160 om541 ci 8602 gn block diagram 5401 DM transistor 74L10 74S136
Contextual Info: N ational Semiconductor Section 1 - 54/74 SSI DEVICES Connection Diagram s • Electrical Tables Section 2 - 54/74 M SI DEVICES Section 3 - National Semiconductor PROPRIETARY DEVICES Section 4 - National Semiconductor ADDITIONAL D EV KES t o NATIONAL Manufactured under one or more of the fo llowing U.S. patents: 3083262, 3189758, 3231797 , 3303356, 3317671, 3323071, 3381071, 3408542, 3421025, 3426423, 3440498, 3518750, 3519897, 3557431, 3560765,

dm8130

Abstract: 54175 DM74367 KS 2102 7486 ic truth table signetics 2502 ci 8602 gn block diagram ci 8602 gn 74s281 DM74LS76
Contextual Info: 19 7 6 N atio n al S e m ico n d u cto r C o rp . p 1 ? I m • ' % TTL Data Book D EV IC E MIL i 2502 2503 2504 5400 54H00 54L00 54LS00 5401 54H01 54L01 54LS01 5402 54L02 54LS02 5403 54L03 54LS03 5404 54H04 54L04 54LS04 5405 54H05 54L05 54LS05 5406 5407 5408

74HC138

Abstract: block diagram of 74LS138 3 to 8 decoder connection diagram of ic 74ls138 ic 74HC138 M54HC138 M74HC138 FUNCTIONAL APPLICATION OF 74LS138 block diagram of 74LS138 1 line to 16 line and gate 74LS138
Contextual Info: M54HC138 M74HC138 SGS-THOMSON m 3 TO 8 LINE DECODER INVERTING • HIGH SPEED t PD= 17ns (TYP.) at VCc = 5V ■ LOW POWER DISSIPATION Icc = 4 ¡iA at Ta = 25°C ■ OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS ■ BALANCED PROPAGATION DELAYS tpLH= tpHL ■ SYMMETRICAL OUTPUT IMPEDANCE

spice 74ls00

Contextual Info: CircuitMaker for Windows Integrated Schematic Capture and Circuit Simulation User Manual CircuitMaker 6 CircuitMaker PRO Revision C Information in this document is subject to change without notice and does not represent a commitment on the part of MicroCode Engineering. The software described in this document is

cn/74HC138

Contextual Info: _ 5 b E D • 7 cIBliS37 0 0 3 ^ 6 ^1 flflS ■ S G T H _ / T T SGS-1HOMSON ^7# [10«»i gTOKl S M54HC138 M74HC138 S G S-TH0HS0N T'4T~2t-S~S‘ 3 TO 8 LINE DECODER (INVERTING ■ HIGH SPEED tPD= 17ns (TYP.) at VCc = 5V ■ LOW POWER DISSIPATION

74HC138

Abstract: CI 74LS138 ic 74HC138 pin diagram of ic 74ls138 block diagram of 74LS138 3 to 8 decoder FUNCTIONAL APPLICATION OF 74LS138 block diagram of 74LS138 1 line to 16 line M54HC138 M74HC138 connection diagram of ic 74ls138
Contextual Info: S G S -T H O M S O N M igtM m iO TM O gS M 54HC138 M 74HC138 3 TO 8 LINE DECODER INVERTING • HIGH SPEED tPD= 17ns (TYP.) at VCc = 5V ■ LOW POW ER DISSIPATION Ic e = 4 /.A at TA = 2 5 °C ■ OU TPUT DRIVE CAPABILITY 10 LSTTL LOADS ■ BALANCED PROPAGATION DELAYS

Contextual Info: C T S C S -T H O M S O N *7# dO g[i3 iLi(gra at VCc = 5V ■ LOW POWER DISSIPATION Ice = 4 at TA = 25°C ■ OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS ■ BALANCED PROPAGATION DELAYS

IC 3-8 decoder 74138 pin diagram

Abstract: F9444 MSI IC 74138 decoder power control F9444 F9445 self-test 74138 FAIRCHILD f9445 Fairchild 9445 F9445-16DM 74ls240 bus transfer switch
Contextual Info: FAIRCHILD A Schlumberger Company Preliminary Data Sheet April 1982 Description The F9445 is a 16-bit microprocessor implemented using Fairchild’s Isoplanar Integrated Injection Logic l3L technology. This bipolar technology and a sophisticated pipeline architecture combine to give the F9445 very fast

LM24012A

Abstract: 8051 T6963C T6963C 8051 T6A39FG lm24012 T6A39 8x8 font flowchart of 8051 with lcd LM240128AFG T6963C
Contextual Info:  SPECIFICATION Model: LM240128AFG   LM240128AFG 1. BASIC SPECIFICATIONS 1.1 Display Specifications LCD Mode : STN/Blue/Transmissive Driving Duty : 1/128 Duty Viewing Direction : 6:00 Backlight : CCFL 1.2 Mechanical Specifications Outline Dimension : 154.0 W X 104.0(H) X 15.5(T)

74HC138

Abstract: M54HCT138 M54HCT138F1R M74HCT138 M74HCT138B1R M74HCT138C1R M74HCT138M1R connection diagram of ic 74ls138
Contextual Info: M54HCT138 M74HCT138 3 TO 8 LINE DECODER INVERTING . . . . . . . HIGH SPEED tPD = 16 ns (TYP.) at VCC = 5 V LOW POWER DISSIPATION ICC = 4 µA AT TA = 25 °C OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS BALANCED PROPAGATION DELAYS tPLH = tPHL SYMMETRICAL OUTPUT IMPEDANCE