COSINE SCR Search Results

COSINE SCR Result Highlights (2)

Part	ECAD Model	Manufacturer	Description	Download	Buy
LDC5072EPWRQ1		Texas Instruments	Automotive inductive position sensor front end with sine/cosine interface 16-TSSOP -40 to 160
LDC5071EPWRQ1		Texas Instruments	Automotive inductive position sensor AFE with sine/cosine interface 16-TSSOP -40 to 160

COSINE SCR Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
c2311 Contextual Info: TMC2311 TMC2311 CMOS Fast Cosine Transform Processor 12 Bits, 15 Million Pixels Per Second Description Features The TM C2311, a high-speed algorithm specific ♦ processor, computes the one or two dimensional forward discrete cosine transform DCT of an 8 or 8x8 point array	OCR Scan	TMC2311 C2311, 12-bit C2311 TMC2311R1C TMC2311R1C1 TMC2311R1C2 2311R1C 2311R1C1	PDF
Contextual Info: TMC2311 TMC2311 CMOS Fast Cosine IVansform Processor 12 Bits, 15 Million Pixels Per Second Description Features The TM C2311, a high-speed algorithm specific ♦ Stand alone execution of 8-point forward or inverse ♦ cosine transform Continuous 8x8-point 2-D DCTs every 4.48 ¿is	OCR Scan	TMC2311 C2311, 12-bit TMC2311R1C 2311R1C TMC2311R1C1 2311R1C1 TMC2311R1C2 2311R1C2	PDF
dct verilog code Contextual Info: Ease of Integration & Performance High clock speed >250 MHz in 0.18um ASIC technologies DCT-FI Low gate count 2D Forward and Inverse Discrete Cosine Transform Megafunction The DCT-FI megafunction implements the combined 2D Forward/Inverse Cosine Transforms. Most of the image/video compression standards (JPEG, MPEGx, H.261, H.263,	Original	16x16 dct verilog code	PDF
ADSP-2100 Abstract: ADSP-2101 ADSP-2171 ADSP-21XX "Huffman coding" 513300 Contextual Info: Discrete Cosine Transform 7.1 7 OVERVIEW The Discrete Cosine Transform, or DCT, transforms data into a format that can be easily compressed. The characteristics of the DCT make it ideally suited for image compression algorithms. These algorithms let you minimize the amount of data needed to recreate a digitized image.	Original		PDF
dct verilog code Abstract: verilog code DCT 2d dct block verilog code for 8x8 Contextual Info: Ease of Integration & Performance  High clock speed >250 MHz in 0.18um ASIC technologies DCT  Low gate count  Single clock cycle per sample 2-D Forward Discrete Cosine Transform Core operation  Low latency (87 cycles) Design Quality The DCT core implements the 2D Forward Cosine Transform. Most of the image/video	Original	16x16 dct verilog code verilog code DCT 2d dct block verilog code for 8x8	PDF
IQ generator Abstract: AN1946 quadrature bridge APP1946 MAX4454 Contextual Info: Maxim > App Notes > WIRELESS, RF, AND CABLE Keywords: i/q, in, phase, quadrature, sine, cosine, generator, op, amp, 90, rf, rfic Mar 25, 2003 APPLICATION NOTE 1946 A MAX4454-based IQ Generator Tests RF Quadrature Modulators Abstract: This app note describes a simple, low-cost, sine-cosine generator that can be used for testing	Original	MAX4454-based MAX4454 65kHz -46dBc. com/an1946 MAX4454: AN1946, APP1946, Appnote1946, IQ generator AN1946 quadrature bridge APP1946 MAX4454	PDF
Am29540 Contextual Info: Am29526 • Am29527 Am29528 • Am29529 High Speed Sine, Cosine Generators D ISTINC TIVE C H A R A C TE R IS TIC S FU N C T IO N A L DESCR IPTIO N • Provides values for sine/cosine functions in 7J-/2048 increm ents • Outputs are 16-bit tw o's com plem ent fractions	OCR Scan	Am29526 Am29527 Am29528 Am29529 7J-/2048 16-bit tt/2048. 11-bit IL-STD-883, Am29540	PDF
IDCT design FPGA Abstract: dct verilog code Contextual Info: Ease of Integration & Performance  High clock speed >250 MHz in 0.18um ASIC technologies IDCT  Low gate count  Single clock cycle per sample 2-D Inverse Discrete Cosine Transform Core operation  Low latency (86 cycles) Design Quality The IDCT core implements the 2D Inverse Cosine Transform. Most of the image/video	Original	16x16 IDCT design FPGA dct verilog code	PDF
AN1946 Abstract: APP1946 MAX4454 OPAMP RF MODULATOR Contextual Info: Maxim > App Notes > Wireless and RF Keywords: i/q, in, phase, quadrature, sine, cosine, generator, op, amp, 90, rf, rfic Mar 25, 2003 APPLICATION NOTE 1946 A MAX4454-based I/Q generator tests RF quadrature modulators Abstract: This application note describes a simple, low-cost, sine-cosine generator that can be used for testing quadrature	Original	MAX4454-based MAX4454 MAX4454 200MHz, com/an1946 AN1946, APP1946, Appnote1946, AN1946 APP1946 OPAMP RF MODULATOR	PDF
P241A Abstract: AM29526PC AM29526PC-B AM29527PC AM29528PC AM29529PC Contextual Info: Am29526 • Am29527 Am29528 • Am29529 H ig h Speed Sine, Cosine Generators D ISTINC TIVE C H A R A C TER ISTIC S FU N C TIO N A L DESCR IPTION • Provides values for sine/cosine functions in 77/2048 increm ents • O utputs are 16-bit tw o's com plem ent fractions	OCR Scan	Am29526 Am29527 Am29528 Am29529 w/204S 16-bit Am29516/17 Am29510 P241A AM29526PC AM29526PC-B AM29527PC AM29528PC AM29529PC	PDF
dct verilog code Contextual Info: Ease of Integration & Performance  High clock speed >250 MHz in 0.18um ASIC technologies DCT  Low gate count  Single clock cycle per sample 2-D Forward Discrete Cosine Transform Core operation  Low latency (87 cycles) Design Quality The DCT core implements the 2D Forward Cosine Transform. Most of the image/video	Original	16x16 dct verilog code	PDF
dct verilog code Abstract: IDCT xilinx Contextual Info: Ease of Integration & Performance  High clock speed >250 MHz in 0.18um ASIC technologies IDCT  Low gate count  Single clock cycle per sample 2-D Inverse Discrete Cosine Transform Core operation  Low latency (86 cycles) Design Quality The IDCT core implements the 2D Inverse Cosine Transform. Most of the image/video	Original	16x16 dct verilog code IDCT xilinx	PDF
half adder ttl Abstract: column-major TMC2311 adder-subtractor design TMC2312 DIN11 TMC2220 TMC2250 TMC2272 "Huffman coding" Contextual Info: TMC2311 C M O S Fast Cosine Transform Processor 12 Bits, 15 Million Pixels Per Second The TMC2311, a high-speed algorithm specific processor, computes the one or tw o dimensional forward discrete cosine transform DCT of an 8 or 8x8 point array of contiguous 9-bit data or the inverse DCT of 12-bit data.	OCR Scan	TMC2311 TMC2311, 12-bit TMC2311 2311R1C2 half adder ttl column-major adder-subtractor design TMC2312 DIN11 TMC2220 TMC2250 TMC2272 "Huffman coding"	PDF
TGA1230 Abstract: signal generator tga1230 Thurlby wave2 30Mhz oscilloscope 40VA EN50081-1 EN50082-1 EN61010-1 IEEE488 Contextual Info: CYAN MAGENTA YELLOW BLACK Technical Specifications Technical Specifications continued ARBITRARY WAVEFORM EDITING WAVEFORMS MODULATION MODES Standard Waveforms Triggered Burst Sine, square, triangle, DC, positive ramp, negative ramp, sin x /x, pulse, pulse train, cosine, haversine and havercosine.	Original	Have40oC, -20oC IEEE-488 EN61010-1. EN50081-1 EN50082-1. 30MS/s, 12-bit, TGA1230 signal generator tga1230 Thurlby wave2 30Mhz oscilloscope 40VA EN50082-1 EN61010-1 IEEE488	PDF

rAised cosine FILTER Abstract: RC filter 210E DECIMATION IN FREQUENCY DSP raised cosine HSP43124 HSP50110 HSP50210 c code iir filter design Contextual Info: TM Loading Custom Digital Filters Into the HSP50110/210EVAL Application Note January 1999 Introduction AN9676.1 Root-Raised Cosine Background Information The HSP50110/210EVAL was intended to showcase the demodulation capabilities of the HSP50110 Digital Quadrature	Original	HSP50110/210EVAL AN9676 HSP50110/210EVAL HSP50110 HSP50210 10-bit 52MHz. rAised cosine FILTER RC filter 210E DECIMATION IN FREQUENCY DSP raised cosine HSP43124 c code iir filter design	PDF
16 QAM receiver block diagram Abstract: amplifier equalizer mixer connection diagram receiver QAM schematic diagram digital clock and carrier recovery 32 QAM BER SER 32QAM modulation TDA8045H 64 QAM diagram 16 qam demodulator carrier recovery Contextual Info: Preliminary specification Philips Semiconductors QAM demodulator TDA8045 FEATURES • Different modulation schemes: 4, 16, 32 and 64-QAM • Digital demodulator and Square-Root Raised-Cosine Nyquist filter with roll-off of 20% • High performance adaptive equalizer no training	OCR Scan	TDA8045 64-QAM 711002b 16 QAM receiver block diagram amplifier equalizer mixer connection diagram receiver QAM schematic diagram digital clock and carrier recovery 32 QAM BER SER 32QAM modulation TDA8045H 64 QAM diagram 16 qam demodulator carrier recovery	PDF
SFSH Abstract: MX919B MX919BDS MX919BDW MX919BLH MX919BP Contextual Info: MX919B COMMUNICATION SEMICONDUCTORS DATA BULLETIN 4-Level FSK Modem Data Pump PRELIMINARY INFORMATION Features Applications • 4-Level Root Raised Cosine FSK Modulation • Wireless Data Terminals • Half Duplex, 4800 to 19.2kbps • Two Way Paging Systems	Original	MX919B 24-pin MX919BP SFSH MX919B MX919BDS MX919BDW MX919BLH MX919BP	PDF
fsk modulator using 555 Abstract: PLC modem plc modem using fsk X25 crc fsk modem MX 128 D MX919B MX919BDS MX919BDW MX919BLH Contextual Info: MX919B COMMUNICATION SEMICONDUCTORS DATA BULLETIN 4-Level FSK Modem Data Pump PRELIMINARY INFORMATION Features Applications • 4-Level Root Raised Cosine FSK Modulation • Wireless Data Terminals • Half Duplex, 4800 to 19.2kbps • Two Way Paging Systems	Original	MX919B fsk modulator using 555 PLC modem plc modem using fsk X25 crc fsk modem MX 128 D MX919B MX919BDS MX919BDW MX919BLH	PDF
Contextual Info: MX919B COMMUNICATION SEMICONDUCTORS DATA BULLETIN 4-Level FSK Modem Data Pump PRELIMINARY INFORMATION Features Applications • 4-Level Root Raised Cosine FSK Modulation • Wireless Data Terminals • Half Duplex, 4800 to 19.2kbps • Two Way Paging Systems	Original	MX919B	PDF
B7AB Abstract: Optical Electronics "optical electronics" Contextual Info: OPTICAL ELECTRONICS INC ObE D \| bTnaflb DODlfibA □ \| 5090A DATA AND SPECIFICATIONS DESCRIPTION AND INSTRUCTIONS Optical Electronics Incorporated T-73-W POLAR-TO-CARTESIAN COORDINATE CONVERTER FEATURES • R sin 0, R cosine 0 • FREQUENCY RESPONSE: DC-300KHZ	OCR Scan	T-73-V/ DC-300KHZ B7AB Optical Electronics "optical electronics"	PDF
verilog for 8 point dct in xilinx Abstract: XAPP208 fir filter spartan 3 fir filter design using vhdl verilog 2d filter xilinx Contextual Info: 1-D Discrete Cosine Transform DCT V2.1 March 14, 2002 Product Specification General Description Xilinx Inc. 2100 Logic Drive San Jose, CA 95124 Phone: +1 408-559-7778 Fax: +1 408-559-7114 URL: www.xilinx.com/ipcenter Support: support.xilinx.com Features	Original	24-bit com/xapp/xapp208 verilog for 8 point dct in xilinx XAPP208 fir filter spartan 3 fir filter design using vhdl verilog 2d filter xilinx	PDF
VHDL code DCT Abstract: vhdl code for multiplexer 8 to 1 using 2 to 1 vhdl code for inverse matrix idct vhdl code verilog code for inverse matrix vhdl code for transpose memory vhdl code for matrix multiplication matrix multiplier Vhdl code verilog code for 16*16 multiplier matrix multiplication code in vhdl with testbench file Contextual Info: FIDCT Forward/Inverse Discrete Cosine Transform December 5, 2000 Product Specification AllianceCORE Facts Tilab Via G. Reiss Romoli, 274 10148 Torino, Italy Phone: +39 011 228 5659 Fax: +39 011 228 7140 E-mail: viplibrary@tilab.com URL: www.telecomitalialab.com	Original	16x16 VHDL code DCT vhdl code for multiplexer 8 to 1 using 2 to 1 vhdl code for inverse matrix idct vhdl code verilog code for inverse matrix vhdl code for transpose memory vhdl code for matrix multiplication matrix multiplier Vhdl code verilog code for 16*16 multiplier matrix multiplication code in vhdl with testbench file	PDF
BER SER 32QAM modulation Abstract: TDA8045 32 QAM quadrant detector 9923E 64 QAM diagram carrier recovery philips ir demodulator qam demodulator QFP64 Contextual Info: Philips Semiconductors Preliminary specification QAM demodulator TDA8045 FEATURES • Different modulation schemes: 4, 16, 32 and 64-QAM • Digital demodulator and Square-Root Raised-Cosine Nyquist filter with roll-off of 20% • High performance adaptive equalizer no training	OCR Scan	TDA8045 64-QAM 711062b BER SER 32QAM modulation TDA8045 32 QAM quadrant detector 9923E 64 QAM diagram carrier recovery philips ir demodulator qam demodulator QFP64	PDF
vhdl code for matrix multiplication Abstract: VHDL code DCT vhdl code for inverse matrix vhdl code for transpose memory vhdl coding for pipeline matrix multiplication code in vhdl with testbench file verilog code for 8x8 matrix multiplication matrix multiplier Vhdl code idct vhdl code verilog code for matrix multiplication Contextual Info: FIDCT Forward/Inverse Discrete Cosine Transform September 18, 2000 Product Specification AllianceCORE Facts CSELT S.p.A Via G. Reiss Romoli, 274 I-10148 Torino, Italy Phone: +39 011 228 5259 Fax: +39 011 228 5695 E-mail: viplibrary@cselt.it URL: www.cselt.it	Original	I-10148 16x16 vhdl code for matrix multiplication VHDL code DCT vhdl code for inverse matrix vhdl code for transpose memory vhdl coding for pipeline matrix multiplication code in vhdl with testbench file verilog code for 8x8 matrix multiplication matrix multiplier Vhdl code idct vhdl code verilog code for matrix multiplication	PDF

COSINE SCR Search Results

COSINE SCR Result Highlights (2)

COSINE SCR Datasheets Context Search

c2311

dct verilog code

ADSP-2100

dct verilog code

IQ generator

Am29540

IDCT design FPGA

AN1946

P241A

dct verilog code

dct verilog code

half adder ttl

TGA1230

rAised cosine FILTER

16 QAM receiver block diagram

SFSH

fsk modulator using 555

B7AB

verilog for 8 point dct in xilinx

VHDL code DCT

BER SER 32QAM modulation

vhdl code for matrix multiplication