CY7C1049L Search Results

CY7C1049

Abstract: CY7C1049L
Contextual Info: fax id: 1082 S b M IM Ì F T V fS T“ ¡T* &*• r i s I a ÆÊ l i i J F ; U F lm CY7C1049 CY7C1049L PRELIMINARY ß b ö 512 K x 8 Static RAM Features is provided by an active LOW chip enable CE , an active LOW output enable (OE), and three-state drivers. Writing to the de­

CY7C1049-17VC

Abstract: t 1049 CY7C1049 CY7C1049-15VC 7C1049-20
Contextual Info: fax id: 1082 1CY 7C10 49 CY7C1049 CY7C1049L PRELIMINARY 512K x 8 Static RAM Features • High speed — tAA = 17 ns • Low active power — 1073 mW max. • Low CMOS standby power (L version) — 2.75 mW (max.) • 2.0V Data Retention (400 µW at 2.0V retention)

Contextual Info: fax id: 1082 — — • PRELIMINARY CY7C1049 5 1 2K x 8 Static RAM is provided by an active LOW chip enable CE , an active LOW output enable (OE), and three-state drivers. Writing to the de­ vice is accomplished by taking chip enable (CE) and write en­

CY62148

Abstract: CY7C1049
Contextual Info: PRESS RELEASE CYPRESS INTRODUCES 4-MEGABIT SRAMS WITH 26 MILLION TRANSISTORS New Products Showcase Cypress Design and Process Expertise; Broaden SRAM Line SAN JOSE, Calif., September 15, 1997 - Cypress Semiconductor today introduced a family of 4-megabit Static RAMs SRAMs manufactured with Cypress’s leading-edge

Contextual Info: fax id: 1082 W CYPRESS PRELIMINARY 512Kx 8 Static RAM is provided by an active LOW chip enable CE , an active LOW output enable (OE), and three-state drivers. Writing to the de­ vice is accomplished by taking chip enable (CE) and write en­ able (WE) inputs LOW. Data on the eight I/O pins (l/O0 through

CY7C1049

Abstract: CY7C1049-15VC CY7C1049L-15VC
Contextual Info: fax id: 1082 PRELIMINARY CY7C1049 512K x 8 Static RAM Features • High speed — tAA = 15 ns • Low active power — 1210 mW max. • Low CMOS standby power (Commercial L version) — 2.75 mW (max.) • 2.0V Data Retention (400 µW at 2.0V retention) • Automatic power-down when deselected

verilog for SRAM 512k word 16bit

Abstract: CY62512V CYM74P436 192-Macrocell 62128 sram 7C1350 Triton P54C palce16v8 programming guide 7C168A intel 16k 8bit RAM chip
Contextual Info: Product Selector Guide Static RAMs Organization/Density Density X1 X4 4K X8 X9 X16 X18 X32 X36 7C148 7C149 7C150 16K 7C167A 7C168A 7C128A 6116 64K to 72K 7C187 7C164 7C166 7C185 6264 7C182 256K to 288K 7C197 7C194 7C195 7C199 7C1399/V 62256/V 62256V25 62256V18

CY7C1049-20

Contextual Info: fax id: 1082 C Y 7C 1049 CY7C 1049L 512K x 8 Static RAM is provided by an active LOW chip enable CE , an active LOW output enable (OE), and three-state drivers. Writing to the de­ vice is accomplished by taking chip enable (CE) and write en­ able (WE) inputs LOW. Data on the eight I/O pins (l/O0 through

2M X 32 Bits 72-Pin Flash SO-DIMM

Abstract: AN2131QC Triton P54C SO-DIMM 72pin 32bit 5V 2M AN2131-DK001 AN2131SC vhdl code for pipelined matrix multiplication VIC068A user guide parallel interface ts vhdl 7C037
Contextual Info: GO TO WEB MAIN INDEX 3URGXFW 6HOHFWRU *XLGH Static RAMs Organization/Density Overview Density X1 X4 X8 X9 X16 X18 X32 X36 7C148 7C149 7C150 4 Kb 16 Kb 7C167A 7C168A 7C128A 6116 64 Kb to 72 Kb 7C187 7C164 7C166 7C185 6264 7C182 256 Kb to 288 Kb 7C197 7C194

ZL5.6

Abstract: H1311 soj 36 CY7C1049
Contextual Info: fax id: 1082 ; ; ; -Hi ' .üÉÉÉÉÉÉÉÉÉÉiüüiüHjjju'.' ; : ; IS. . : : : : : : ; ; ; ; : ; ;' : : : CY7C1049 P R E L IM IN A R Y •rriM U M iM iiiu m m r t V - § « < !N : 5 1 2 K x 8 Static RAM Features is provided by an active LOW chip enable CE , an active LOW

CY7C1049

Abstract: CY7C1049-15VC CY7C1049L-15VC
Contextual Info: 049 PRELIMINARY CY7C1049 512K x 8 Static RAM Features • High speed — tAA = 15 ns • Low active power — 1210 mW max. • Low CMOS standby power (Commercial L version) — 2.75 mW (max.) • 2.0V Data Retention (400 µW at 2.0V retention) • Automatic power-down when deselected

Contextual Info: fax id: 1082 PRELIMINARY CY7C1049 512Kx 8 Static RAM Features is provided by an active LOW chip enable CE , an active LOW output enable (OE), and three-state drivers. Writing to the de­ vice is accomplished by taking chip enable (CE) and write en­ able (WE) inputs LOW. Data on the eight I/O pins (I/O q through

CY7C1049

Abstract: CY7C1049-15VC CY7C1049L-15VC
Contextual Info: 049 PRELIMINARY CY7C1049 512K x 8 Static RAM Features • High speed — tAA = 15 ns • Low active power — 1210 mW max. • Low CMOS standby power (Commercial L version) — 2.75 mW (max.) • 2.0V Data Retention (400 µW at 2.0V retention) • Automatic power-down when deselected

DSLAM structure

Abstract: SWITCHING TRANSISTOR C145 design of interfacing circuit Max202 LT1422 DSLAM drawing PMC-1990357 PMC-1990815 PCC1749CT-ND PMC-1990354 Actel A42MX09
Contextual Info: PM7350 S/UNI-DUPLEX PRELIMINARY REFERENCE DESIGN PMC-1990474 ISSUE 3 DSLAM REFERENCE DESIGN: WAN CARD PM7350 DSLAM REFERENCE DESIGN: WAN CARD RELEASED ISSUE 3:NOVEMBER 2000 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE