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CY7C1315CV18 Price and Stock

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Rochester Electronics LLC CY7C1315CV18-250BZC IC SRAM 18MBIT PAR 165FBGA
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DigiKey	CY7C1315CV18-250BZC	Tray	1,840		10	1 - 10 $33.05 100 $33.05 1000 $33.05 10000 $33.05	Buy Now
Rochester Electronics LLC CY7C1315CV18-200BZC IC SRAM 18MBIT PARALLEL 165FBGA
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DigiKey	CY7C1315CV18-200BZC	Tray	407		10	1 - 10 $30.19 100 $30.19 1000 $30.19 10000 $30.19	Buy Now
Rochester Electronics LLC CY7C1315CV18-250BZI IC SRAM 18MBIT PAR 165FBGA
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DigiKey	CY7C1315CV18-250BZI	Tray	379		9	1 - 10 $34.73 100 $34.73 1000 $34.73 10000 $34.73	Buy Now
Rochester Electronics LLC CY7C1315CV18-167BZC IC SRAM 18MBIT PAR 165FBGA
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
DigiKey	CY7C1315CV18-167BZC	Tray	281		10	1 - 10 $30.19 100 $30.19 1000 $30.19 10000 $30.19	Buy Now
Rochester Electronics LLC CY7C1315CV18-250BZXC IC SRAM 18MBIT PAR 165FBGA
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
DigiKey	CY7C1315CV18-250BZXC	Tray	79		10	1 - 10 $33.01 100 $33.01 1000 $33.01 10000 $33.01	Buy Now

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CY7C1315CV18 Datasheets (6)

Part	ECAD Model	Manufacturer	Description	Curated	Datasheet Type	PDF
CY7C1315CV18		Cypress Semiconductor	18-Mbit QDR-II SRAM 4-Word Burst Architecture		Original	PDF
CY7C1315CV18-167BZC		Cypress Semiconductor	18-Mbit QDR -II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 18 Mb; Organization: 512Kb x 36; Vcc (V): 1.7 to 1.9 V		Original	PDF
CY7C1315CV18-200BZC		Cypress Semiconductor	18-Mbit QDR -II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 18 Mb; Organization: 512Kb x 36; Vcc (V): 1.7 to 1.9 V		Original	PDF
CY7C1315CV18-250BZC		Cypress Semiconductor	18-Mbit QDR -II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 18 Mb; Organization: 512Kb x 36; Vcc (V): 1.7 to 1.9 V		Original	PDF
CY7C1315CV18-250BZI		Cypress Semiconductor	18-Mbit QDR -II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 18 Mb; Organization: 512Kb x 36; Vcc (V): 1.7 to 1.9 V		Original	PDF
CY7C1315CV18-250BZXC		Cypress Semiconductor	18-Mbit QDR -II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 18 Mb; Organization: 512Kb x 36; Vcc (V): 1.7 to 1.9 V		Original	PDF

CY7C1315CV18 Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
CY7C1311CV18 Abstract: CY7C1313CV18 CY7C1315CV18 CY7C1911CV18 Contextual Info: CY7C1311CV18, CY7C1911CV18 CY7C1313CV18, CY7C1315CV18 18-Mbit QDR -II SRAM 4-Word Burst Architecture Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 300 MHz clock for high bandwidth ■	Original	CY7C1311CV18, CY7C1911CV18 CY7C1313CV18, CY7C1315CV18 18-Mbit CY7C1311CV18 CY7C1313CV18 CY7C1311CV18 CY7C1313CV18 CY7C1315CV18 CY7C1911CV18	PDF
Contextual Info: CY7C1311CV18 CY7C1911CV18 CY7C1313CV18 CY7C1315CV18 PRELIMINARY 18-Mbit QDR -II SRAM 4-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports • QDR-II operates with 1.5 cycle read latency when the DLL is enabled	Original	CY7C1311CV18 CY7C1911CV18 CY7C1313CV18 CY7C1315CV18 18-Mbit 300-MHz 600MHz)	PDF
Contextual Info: THIS SPEC IS OBSOLETE Spec No: 001-07165 Spec Title: 7C1313CV18/CY7C1315CV18, 18-MBIT QDR R II SRAM 4-WORD BURST ARCHITECTURE Sunset Owner: Jayasree Nayar (NJY) Replaced by: NONE CY7C1313CV18 CY7C1315CV18 18-Mbit QDR II SRAM 4-Word Burst Architecture 18-Mbit QDR® II SRAM 4-Word Burst Architecture	Original	7C1313CV18/CY7C1315CV18, 18-MBIT CY7C1313CV18 CY7C1315CV18	PDF
Contextual Info: CY7C1313CV18 CY7C1315CV18 18-Mbit QDR II SRAM 4-Word Burst Architecture 18-Mbit QDR® II SRAM 4-Word Burst Architecture Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions CY7C1313CV18 – 1M x 18 •	Original	CY7C1313CV18 CY7C1315CV18 18-Mbit CY7C1313CV18	PDF
CY7C1311CV18 Abstract: CY7C1313CV18 CY7C1315CV18 CY7C1911CV18 Contextual Info: CY7C1311CV18, CY7C1911CV18 CY7C1313CV18, CY7C1315CV18 18-Mbit QDR -II SRAM 4-Word Burst Architecture Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 300 MHz clock for high bandwidth ■	Original	CY7C1311CV18, CY7C1911CV18 CY7C1313CV18, CY7C1315CV18 18-Mbit CY7C1311CV18 CY7C1313CV18 CY7C1311CV18 CY7C1313CV18 CY7C1315CV18 CY7C1911CV18	PDF
Contextual Info: CY7C1313CV18 CY7C1315CV18 18-Mbit QDR II SRAM 4-Word Burst Architecture Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions CY7C1313CV18 – 1M x 18 ■ 300 MHz clock for high bandwidth ■ 4-word burst for reducing address bus frequency	Original	CY7C1313CV18 CY7C1315CV18 18-Mbit CY7C1313CV18	PDF