CY7C1329H Search Results

Contextual Info: CY7C1329H 2-Mbit 64 K x 32 Pipelined Sync SRAM 2-Mbit (64 K × 32) Pipelined Sync SRAM Features Functional Description • Registered inputs and outputs for pipelined operation The CY7C1329H SRAM integrates 64 K × 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter

Contextual Info: CY7C1329H PRELIMINARY 2-Mbit 64K x 32 Pipelined Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • 64K x 32 common I/O architecture • 3.3V core power supply • 2.5V I/O operation • Fast clock-to-output times

Contextual Info: CY7C1329H 2-Mbit 64K x 32 Pipelined Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • 64K x 32 common I/O architecture • 3.3V core power supply • 2.5V I/O operation • Fast clock-to-output times

CY7C1329H

Abstract: CY7C1329H-166AXC
Contextual Info: CY7C1329H 2-Mbit 64K x 32 Pipelined Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • 64K x 32 common I/O architecture • 3.3V core power supply • 2.5V/3.3V I/O operation • Fast clock-to-output times

CY7C1329H

Abstract: CY7C1329H-133AXC
Contextual Info: CY7C1329H 2-Mbit 64K x 32 Pipelined Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • 64K x 32 common I/O architecture • 3.3V core power supply • 2.5V/3.3V I/O operation • Fast clock-to-output times

Contextual Info: CY7C1329H 2-Mbit 64 K x 32 Pipelined Sync SRAM 2-Mbit (64 K × 32) Pipelined Sync SRAM Features Functional Description • Registered inputs and outputs for pipelined operation The CY7C1329H SRAM integrates 64 K × 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter

CY7C1329H

Abstract: CY7C1329H-166AXC
Contextual Info: CY7C1329H 2-Mbit 64K x 32 Pipelined Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • 64K x 32 common I/O architecture • 3.3V core power supply • 2.5V/3.3V I/O operation • Fast clock-to-output times

Contextual Info: CY7C1329H 2-Mbit 64 K x 32 Pipelined Sync SRAM 2-Mbit (64 K × 32) Pipelined Sync SRAM Features Functional Description • Registered inputs and outputs for pipelined operation The CY7C1329H SRAM integrates 64 K × 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter

Contextual Info: CY7C1329H 2-Mbit 64 K x 32 Pipelined Sync SRAM 2-Mbit (64 K × 32) Pipelined Sync SRAM Features Functional Description The CY7C1329H[1] SRAM integrates 64 K × 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by

CY7C1329H

Abstract: CY7C1329H-166AXC
Contextual Info: CY7C1329H 2-Mbit 64K x 32 Pipelined Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • 64K x 32 common I/O architecture • 3.3V core power supply • 2.5V/3.3V I/O operation • Fast clock-to-output times

FSQ510 Equivalent

Abstract: BTA12 6008 bta16 6008 ZIGBEE interface with AVR ATmega16 Precision triac control thermostat thyristor t 558 f eupec gw 5819 diode transistor a564 A564 transistor BSM25GP120 b2
Contextual Info: SEMICONDUCTORS MCU/MPU/DSP Atmel. . . . . . . . . 167, 168, 169, 170, 171, 172 Blackhawk. . . . . . . . . . . . . . . . . . . . . . . . . 173 Cyan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Cypress. . . . . . . . . . . . . . . 175, 176, 177, 178