CY7C1335 Search Results

7C13

Abstract: CY7C1335
Contextual Info: fax id: 1045 1CY 7C13 35 PRELIMINARY CY7C1335 32K x 32 Synchronous-Pipelined Cache RAM Features Functional Description • Low 660 µW standby power (f=0, L version) The CY7C1335 is 3.3V 32K by 32 synchronous-pipelined cache SRAM designed to support zero wait state secondary

CY7C1335

Abstract: CY7C1336
Contextual Info: CY7C1335 CY7C1336 ADVANCED INFORMATION 32K x 32 Synchronous Cache RAM D D D Features D Supports 75ĆMHz Pentiumt and PowerPCt operations with zero wait states D Fully registers inputs and outputs for pipelined operation D D D 32K x 32 common I/O architecture

CY7C1335

Abstract: CY7C1336
Contextual Info: CY7C1335 CY7C1336 ADVANCED INFORMATION 32K x 32 Synchronous Cache RAM D D D Features D Supports 75ĆMHz Pentiumt and PowerPCt operations with zero wait states D Fully registers inputs and outputs for pipelined operation D D D 32K x 32 common I/O architecture

Contextual Info: SHHM & PRELIMINARY CY7C1335 32K X 32 Synchronous-Pipelined Cache RAM Features • S u p p o rts 1 0 0-M H z bus fo r P en tiu m and Pow erPC o p e ra tio n s w ith zero w a it states • F ully reg istered inp u ts and o u tp u ts fo r p ip elined o p e r­

CY7C1335

Abstract: CY7C1336 DO30 3Tg 21
Contextual Info: „ ADVANCED INFORMATION CY7C1335 CY7C1336 '# C Y P n h b b 32K x 32 Synchronous Cache RAM Features • Synchronous self-timed writes • Supports 75-MHz Pentium and PowerPC™ operations with zero wait states • Asynchronous output enable • JEDEC-standard 100 TQFP pinout

Contextual Info: CY7C1335 32K X 32 Synchronous-Pipelined Cache RAM Features • Supports 1 00-MHz bus for Pentium and PowerPC operations with zero wait states • Fully registered inputs and outputs for pipelined oper­ ation • 32K by 32 common I/O architecture • Single 3.3V power supply

CEI 23-16

Abstract: CY7C1329 CY7C1335
Contextual Info: CY7C1335 PRELIMINARY 32K X 32 Synchronous-Pipelined Cache RAM Features • Supports 100-MHz bus for Pentium and PowerPC operations with zero wait states • Fully registered inputs and outputs for pipelined oper­ ation • 32K by 32 common I/O architecture

84-1MISR4

Abstract: JESD22 MP-8000 "32K x 32" SRAM
Contextual Info: Cypress Semiconductor Qualification Report QTP# 97145 VERSION 1.1 June, 1999 32K x 32 Synchronous Pipelined Cache RAM CY7C1335/CY7C1337 CYPRESS TECHNICAL CONTACT FOR QUALIFICATION DATA: Ed Russell Reliability Director 408 432-7069 Cypress Semiconductor 32K x 32 Syn. Pipelined Cache RAM

CY7C1335

Abstract: DQ20C ssqc 25
Contextual Info: fax id: 1045 PRELIMINARY —— — Æ jr r ~ 'f V D D 17 Q CY7C1335 Q I 1 IT C O O 32K X 32 Synchronous-Pipelined Cache RAM Functional Description Features • Low 660 j^W sta n d b y p ow er (f=0, L versio n ) • S u p p o rts 7 5 -M H z bus fo r P en tium and Pow erPC ™

CEI 23-16

Abstract: CY7C1335
Contextual Info: CY7C1335 V CYPRESS 32K x 32 Synchronous-Pipelined Cache RAM Features • S u p p o rts 1 0 0-M H z bus fo r Pentium o p e ratio n s w ith zero w ait sta tes and Pow erPC • F ully reg istered inp u ts and o u tp u ts fo r pip elined operatio n • 32K by 32 co m m o n I/O a rch ite ctu re

CY7C1335

Contextual Info: aven’t re CY7C1335 32K x 32 Synchronous-Pipelined Cache RAM All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise is 4.2 ns 133-MHz

Contextual Info: ADVANCED INFORMATION CY7C1335 CY7C1336 32K x 32 Synchronous Cache RAM Features • Synchronous self-timed writes • Asynchronous output enable • JEDEC-standard 100 TQFP pinout • Supports 75-MHz Pentium and PowerPC ™operations with zero wait states

1335L

Abstract: 335L-60 DQ311
Contextual Info: fax id: 1045 ^fewi\V¥i 8;li! PRELIMINARY CY7C1335 \p c ^y ‘ i. p X :, 32K X 32 Synchronous-Pipelined Cache RAM Features Functional Description • L o w 660 |iW s t a n d b y p o w e r (f=0, L v e r s i o n ) • S u p p o r t s 75-M Hz b u s fo r P e n tiu m a n d P o w e rP C ™

C133-10

Abstract: C1336 C133-14 CY7C133 CY7C143 IDT7133 IDT7143
Contextual Info: CY7C133 CY7C143 2K x 16 Dual-Port Static RAM Features Functional Description • True dual-ported memory cells which allow simultaneous reads of the same memory location • 2K x 16 organization • 0.65-micron CMOS for optimum speed/power • High-speed access: 25/35/55 ns

ATPA

Abstract: 7130SA100P 24l01 7C263/4-35C 7164S15Y cy9122-25 7133SA35J 7142sa55 7130sa55p cy2149-45c
Contextual Info: Product Line Cross Reference CYPRESS CYPRESS CYPRESS CYPRESS CYPRESS CY2147-35C CY7C147-35C CY7C147-45C CY7C147-35C CY91L22-35C CY7C122-35C CY2147-45C CY2147-35C CY7C148-35C CY7C148-25C+ CY91L22-45C CY93L422AC CY2147-45C CY7C147-45C CY7C148-45C CY7C148-35C

CY7C201

Contextual Info: THE FOLLOWING THIRD QUARTER REPORT 1996, the sections entitled “To Our Shareholders” and “Market Perspective” may contain forwardlooking statements about the prospects for Cypress as well as the semiconductor industry more generally including without limitation statements about,

128H

Abstract: 140C 8361H CEL9200 JESD22
Contextual Info: Cypress Semiconductor Qualification Report QTP# 97227 VERSION 1.0 June, 1997 100 Pins TQFP Package Cypress Philippines Assembly Cypress Semiconductor Assembly: Cypress Philippines Package: TQFP QTP# 97227, V. 1.0 Page 2 of 4 June, 1997 PLASTIC PACKAGE/ASSEMBLY DESCRIPTION

CY7C133

Abstract: CY7C143 IDT7133 IDT7143
Contextual Info: CY7C133 CY7C143 2K x 16 Dual-Port Static RAM Features Functional Description • True dual-ported memory cells which allow simultaneous reads of the same memory location • 2K x 16 organization • 0.65-micron CMOS for optimum speed/power • High-speed access: 25/35/55 ns

7C13

Abstract: CY7C133 CY7C143 IDT7133 IDT7143 bit-slice C1335
Contextual Info: fax id: 5202 1CY 7C13 3 CY7C133 CY7C143 2K x 16 Dual-Port Static RAM Features Functional Description • True Dual-Ported memory cells which allow simultaneous reads of the same memory location • 2K x 16 organization • 0.65-micron CMOS for optimum speed/power

VIC068A-BC

Abstract: M71079 M7108 CY62256-VC m71070 LOGIC-R31 M72051 m7101 M72038 VIC068A-AC
Contextual Info: CYPRESS SEMICONDUCTOR CORPORATION PRODUCT RELIABILITY REPORT QUARTER 2, 1997 PERFORM PER THE REQUIREMENT OF 25-00008, RELIABILITY MONITOR PROGRAM SPECIFICATION Marc Hartranft QA Engineering Department Manager CYPRESS SEMICONDUCTOR CORPORATION PRODUCT RELIABILITY REPORT

CY7C1335

Abstract: CY7C1337 CY7C1399 "32K x 32" SRAM
Contextual Info: PRESS RELEASE CYPRESS ANNOUNCES NEW SRAMS OPTIMIZED FOR NETWORKING New Six-Transistor Cell Provides High Performance, Low Power, Excellent Reliability SAN JOSE, Calif., June 16, 1997  Cypress Semiconductor Corporation today introduced two new synchronous, pipelined burst static RAMs SRAMs in the 32K x 32

CY62256LL-PC

Abstract: VIC068A-GC VIC64-NC VIC64-UMB PALCE22V10-JI PALC16L8Q PLD VME A113 CY7B923 JESD22-A113
Contextual Info: Cypress Semiconductor Product Reliability 1997 Published June, 1997 CYPRESS SEMICONDUCTOR PRODUCT RELIABILITY TABLE OF CONTENTS 1.0 OVERVIEW OF CYPRESS SEMICONDUCTOR TOTAL QUALITY MANAGEMENT SYSTEM. 1 2.0 ELECTRICAL AVERAGE OUTGOING QUALITY. 2

CY7C133

Abstract: CY7C143
Contextual Info: CY7C133 CY7C143 2K x 16 Dual-Port Static RAM Features Functional Description • True dual-ported memory cells which allow simultaneous reads of the same memory location • 2K x 16 organization • 0.65-micron CMOS for optimum speed/power • High-speed access: 25/35/55 ns

EPM5128LC

Abstract: IDT CYPRESS CROSS REFERENCE clocks epm5064lc-1 EPM5128LC-1 EPM5064LC EPM5128LC-2 EPM5128GI EPM5128JC-1 8464c 5962-8871309
Contextual Info: Product Line Cross Reference CYPRESS CYPRESS CYPRESS CYPRESS CYPRESS CY2148-35C CY21L48-35C CY7C168A-35C CY7C168A-25C 5962-8871309XX 5962-89839112X CY2148-35C CY7C148-35C CY7C168A-45M CY7C168A-35M+ 5962-8871310RX 5962-8983913RX CY2148-35M CY7C148-35M CY7C169A-35C