CY7C134 Search Results

Contextual Info: CY7C1346H 2-Mbit 64K x 36 Pipelined Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • 64K x 36 common I/O architecture • 3.3V core power supply • 3.3V/2.5V I/O operation • Fast clock-to-output times

CY7C1347

Abstract: CY7C1347-166AC
Contextual Info: CY7C1347 V CYPRESS 128K X 36 Synchronous-Pipelined Cache RAM T he CY7C1347 I/O pins can operate at eith e r the 2.5V or the 3.3V level, the I/O pins are 3.3V to le ra n t w h en V ddq =2.5V. Features • S u p p o rts 1 0 0-M H z bus fo r Pentium o p e ratio n s w ith zero w ait sta tes

Contextual Info: CY7C1347G 4-Mbit 128 K x 36 Pipelined Sync SRAM 4-Mbit (128 K × 36) Pipelined Sync SRAM Features Functional Description • Fully registered inputs and outputs for pipelined operation ■ 128 K × 36 common I/O architecture ■ 3.3 V core power supply (VDD)

L133A

Contextual Info: CY7C1346 64K X 36 Synchronous-Pipelined Cache RAM Features The C Y 7 C 1 346 I/O pins can op era te at eith er the 2.5V o r the 3.3V level; the I/O pins are 3.3 V to le ra n t w h en V DDQ=2.5V. • Supports 10O-MHz bus for Pentium and PowerPC operations with zero wait states

Contextual Info: fax id: 1110 CY7C1344 :/ C Y P R E S S 64K x 36 Synchronous Flow-Through 3.3V Cache RAM Features Functional Description • S u p p o rts 1 1 7 -M H z m ic ro p ro c e s s o r cache s y ste m s w ith zero w a it states • 64K by 36 co m m on I/O • Low S ta n d b y Pow er 1.65 mW, L ve rs io n

CY7C1345

Contextual Info: 345 CY7C1345 128K x 36 Synchronous Flow-Through 3.3V Cache RAM Features Functional Description • Supports 117-MHz microprocessor cache systems with zero wait states • 128K by 36 common I/O • Fast clock-to-output times — 7.5 ns 117-MHz version • Two-bit wrap-around counter supporting either

CY7C1347B

Abstract: memory depth expansion
Contextual Info: CY7C1347 CY7C1347B 128K x 36 Synchronous-Pipelined Cache RAM Features The CY7C1347B I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when VDDQ = 2.5V. • Supports 100-MHz bus for Pentium  and PowerPC operations with zero wait states

CY7C1347D

Abstract: CY7C1347D-225BGC CY7C1347D-250AC CY7C1347D-250BGC
Contextual Info: 327 CY7C1347D 128K x 36 Synchronous-Pipelined Cache SRAM Features • • • • • • • • • • • • • • • • • • • Fast access times: 2.5 and 3.5 ns Fast clock speed: 250, 225, 200, and 166 MHz 1.5 ns set-up time and 0.5 ns hold time

CY7C1328A

Abstract: GVT71256F18
Contextual Info: 327 CY7C1328A/GVT71256F18 CY7C1348A/GVT71128F36 128K x 36/256K x 18 Synchronous-Pipelined Cache RAM Features • • • • • • • • • • • • • • • • • Fast access times: 3.5, 3.8, and 4.0 ns Fast clock speed: 166, 150, 133, and 117 MHz

CY7C1342

Abstract: CY7C135
Contextual Info: 342 and 4K x 8 Dual-Port Static RAM with Semaphores CY7C135 CY7C1342 4K x 8 Dual-Port Static RAMs and 4K x 8 Dual-Port Static RAM with Semaphores Features • True Dual-Ported memory cells which allow simultaneous reads of the same memory location • 4K x 8 organization

Contextual Info: 346A PRELIMINARY CY7C1346A/GVT7164D36 64K x 36 Synchronous Pipelined Burst SRAM Features • • • • • • • • • • • • • • • • • The CY7C1346A/GVT7164D36 SRAM integrates 65,536x36 SRAM cells with advanced synchronous peripheral circuitry

CY7C1346H

Abstract: CY7C1346H-166AXC
Contextual Info: CY7C1346H 2-Mbit 64K x 36 Pipelined Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • 64K x 36 common I/O architecture • 3.3V core power supply • 3.3V/2.5V I/O operation • Fast clock-to-output times

Contextual Info: CY7C1347G 4-Mbit 128 K x 36 Pipelined Sync SRAM 4-Mbit (128 K × 36) Pipelined Sync SRAM Features Functional Description • Fully registered inputs and outputs for pipelined operation ■ 128 K × 36 common I/O architecture ■ 3.3 V core power supply (VDD)

CY7C1340F

Abstract: CY7C1340F-200AC CY7C1340F-200AI CY7C1340F-225AC CY7C1340F-225AI CY7C1340F-250AC CY7C1340F-250AI
Contextual Info: CY7C1340F 4-Mb 128K x 32 Pipelined DCD Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect) — Depth expansion without wait state • 128K x 32-bit common I/O architecture

CY7C1347G-133AXI

Abstract: CY7C1347G-166BGC CY7C1347G CY7C1347G-200AXC CY7C1347G-200BGC CY7C1347G-225AXC CY7C1347G-250AXC CY7C1347G-250BGC
Contextual Info: PRELIMINARY CY7C1347G 4-Mbit 128K x 36 Pipelined Sync SRAM Functional Description[1] Features • Fully registered inputs and outputs for pipelined operation • 128K by 36 common I/O architecture • 3.3V core power supply • 2.5V/3.3V I/O operation • Fast clock-to-output times

sem 2005

Abstract: CY7C1342 CY7C135
Contextual Info: CY7C135 CY7C1342 4K x 8 Dual-Port Static RAM and 4K x 8 Dual-Port SRAM with Semaphores Features Functional Description • True Dual-Ported memory cells which allow simultaneous reads of the same memory location • 4K x 8 organization • 0.65-micron CMOS for optimum speed/power

Contextual Info: CY7C1346H 2-Mbit 64K x 36 Pipelined Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • 64K x 36 common I/O architecture • 3.3V core power supply • 3.3V/2.5V I/O operation • Fast clock-to-output times

Contextual Info: CY7C135, CY7C135A CY7C1342 4K x 8 Dual-Port Static RAM and 4K x 8 Dual-Port SRAM with Semaphores Features Functional Description • True dual-ported memory cells, which allow simultaneous reads of the same memory location ■ 4K x 8 organization ■ 0.65 micron CMOS for optimum speed and power

CY7C1347F

Abstract: CY7C1347F-200AC CY7C1347F-225AC CY7C1347F-225BGC CY7C1347F-250AC CY7C1347F-250BGC
Contextual Info: CY7C1347F 4-Mbit 128K x 36 Pipelined Sync SRAM Functional Description[1] Features • Fully registered inputs and outputs for pipelined operation • 128K by 36 common I/O architecture The CY7C1347F is a 3.3V, 128K by 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache

CY7C1347

Contextual Info: CY7C1347 128K x 36 Synchronous-Pipelined Cache RAM Features The CY7C1347 I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when VDDQ = 2.5V. • Supports 100-MHz bus for Pentium and PowerPC operations with zero wait states

99503

Abstract: 8361H CY7C1339B CY7C1325B CY7C1327B CY7C1329 CY7C1338B CY7C1345B CY7C1347B 619911-1
Contextual Info: Cypress Semiconductor Product Qualification Report QTP# 99503VERSION 2.0 October, 2000 4 Meg Synchronous Cache RAM R52D-3 Technology at Fab 4 CY7C1325B 256K x 18 Synchronous Flow-Through Cache RAM CY7C1327B 256K x 18 Synchronous Pipelined Cache RAM CY7C1345B

Contextual Info: CY7C1345G 4-Mbit 128 K x 36 Flow-Through Sync SRAM 4-Mbit (128 K × 36) Flow through Sync SRAM Functional Description Features • 128 K × 36 common I/O ■ 3.3 V core power supply (VDD) ■ 2.5 V or 3.3 V I/O supply (VDDQ) ■ Fast clock-to-output times

Contextual Info: CY7C1347G 4-Mbit 128 K x 36 Pipelined Sync SRAM 4-Mbit (128 K × 36) Pipelined Sync SRAM Features Functional Description • Fully registered inputs and outputs for pipelined operation ■ 128 K × 36 common I/O architecture ■ 3.3 V core power supply (VDD)

Contextual Info: CY7C1345G 4-Mbit 128 K x 36 Flow-Through Sync SRAM 4-Mbit (128 K × 36) Flow through Sync SRAM Features Functional Description • 128 K × 36 common I/O ■ 3.3 V core power supply (VDD) ■ 2.5 V or 3.3 V I/O supply (VDDQ) ■ Fast clock-to-output times