CY7C1393JV18 Search Results

CY7C1393JV18 Price and Stock

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Infineon Technologies AG CY7C1393JV18-300BZXC IC SRAM 18MBIT PARALLEL 165FBGA
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
DigiKey	CY7C1393JV18-300BZXC	Tray				1 - 10 - 100 - 1000 - 10000 -	Buy Now
Rochester Electronics LLC CY7C1393JV18-300BZXC IC SRAM 18MBIT PARALLEL 165FBGA
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
DigiKey	CY7C1393JV18-300BZXC	Tray			8	1 - 10 $37.55 100 $37.55 1000 $37.55 10000 $37.55	Buy Now
Cypress Semiconductor CY7C1393JV18-300BZXC CY7C1393JV18-300BZXC
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
Verical	CY7C1393JV18-300BZXC		144		9	1 - 10 $45.1375 100 $42.425 1000 $38.3625 10000 $38.3625	Buy Now
	CY7C1393JV18-300BZXC		100		9	1 - 10 $45.1375 100 $42.425 1000 $38.3625 10000 $38.3625	Buy Now
Rochester Electronics	CY7C1393JV18-300BZXC		244		1	1 $36.11 10 $36.11 100 $33.94 1000 $30.69 10000 $30.69	Buy Now

CY7C1393JV18 Datasheets (1)

Part	ECAD Model	Manufacturer	Description	Curated	Datasheet Type	PDF
CY7C1393JV18-300BZXC		Cypress Semiconductor	18-Mbit DDR-II SIO SRAM 2-Word Burst Architecture; Architecture: DDR-II SIO, 2 Word Burst; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 1.7 to 1.9 V		Original	PDF

CY7C1393JV18 Datasheets Context Search

Catalog Datasheet	MFG & Type	PDF	Document Tags
AN5062 Abstract: No abstract text available Text: THIS SPEC IS OBSOLETE Spec No: 001-44698 Spec Title: CY7C1393JV18 CY7C1394JV18, 18 MBIT DDR II SIO SRAM TWO WORD BURST ARCHITECTURE Sunset Owner: N Vijay Kumar VKN Replaced by: None CY7C1393JV18 CY7C1394JV18 18 Mbit DDR II SIO SRAM Two Word Burst Architecture	Original	PDF	CY7C1393JV18 CY7C1394JV18, CY7C1394JV18 CY7C1393JV18, CY7C1394JV18 AN5062
Untitled Abstract: No abstract text available Text: CY7C1393JV18 CY7C1394JV18 18 Mbit DDR II SIO SRAM Two Word Burst Architecture Features Functional Description • 18 Mbit Density 1M x 18, 512K x 36 ■ 300 MHz Clock for High Bandwidth ■ Two word Burst for reducing Address Bus Frequency ■ Double Data Rate (DDR) Interfaces	Original	PDF	CY7C1393JV18 CY7C1394JV18
Untitled Abstract: No abstract text available Text: CY7C1392JV18/CY7C1992JV18 CY7C1393JV18/CY7C1394JV18 18-Mbit DDR II SIO SRAM 2-Word Burst Architecture Features Functional Description • 18- Mbit Density 2M x 8, 2M x 9, 1M x 18, 512K x 36 ■ 300 MHz Clock for High Bandwidth ■ 2-word Burst for reducing Address Bus Frequency	Original	PDF	CY7C1392JV18/CY7C1992JV18 CY7C1393JV18/CY7C1394JV18 18-Mbit CY7C1392JV18, CY7C1992JV18, CY7C1393JV18, CY7C1394JV18
Untitled Abstract: No abstract text available Text: CY7C1392JV18, CY7C1992JV18 CY7C1393JV18, CY7C1394JV18 18-Mbit DDR-II SIO SRAM 2-Word Burst Architecture Features Functional Description • 18- Mbit Density 2M x 8, 2M x 9, 1M x 18, 512K x 36 ■ 300 MHz Clock for High Bandwidth ■ 2-word Burst for reducing Address Bus Frequency	Original	PDF	CY7C1392JV18, CY7C1992JV18 CY7C1393JV18, CY7C1394JV18 18-Mbit CY7C1992JV18, CY7C1394JV18