CY7C264 Search Results

CY7C263-35PC

Abstract: 7C261 CY7C263 CY7C26345DMB cerdip z PACKAGE 7C264 C261 CY7C261 CY7C264 f1b0
Contextual Info: CY7C261 CY7C263/CY7C264 CYPRESS Features • CMOS for optimum speed/power • Windowed for reprogrammability • High speed — 20 ns commercial — 25 ns (military) • Low power — 660 mW (commercial) — 770 m\V (military) • Super low standby power (7C261)

Contextual Info: CY7C2642KV18/CY7C2644KV18 144-Mbit QDR II+ SRAM Two-Word Burst Architecture 2.0 Cycle Read Latency with ODT 144-Mbit QDR ® II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT Features • Separate independent read and write data ports

Contextual Info: pypppqc ' CY7C261 CY7C263/CY7C264 — 8192 x 8 PROM Power Switched and Reprogrammable SEMICONDUCTOR Features • C M O S for optimum speed/pow er • Direct replacement for bipolar PROM s • Windowed for reprogrammability • Capable o f withstanding > 2000V

Contextual Info: CY7C2644KV18 144-Mbit QDR II+ SRAM Two-Word Burst Architecture 2.0 Cycle Read Latency with ODT 144-Mbit QDR ® II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT Features Configurations Separate independent read and write data ports

Contextual Info: CY7C261 CY7C263/CY7C264 8K x 8 Power-Switched and Reprogrammable PROM Features the CY7C261 automatically powers down into a low-power standby mode. It is packaged in a 300-mil-wide package. The CY7C263 and CY7C264 are packaged in 300-mil-wide and 600-mil-wide packages respectively, and do not power down

smd code ND

Abstract: 7c263 L43 SMD
Contextual Info: CY7C261 CY7C263/CY7C264 CYPRESS SEMICONDUCTOR • TTL-compatlble I/O • Direct replacement for bipolar PROMs • CMOS for optimum speed/power • Windowed Tor reprogrammability • High speed — 20 ns commercial — 25 ns (military) • Low power — 660 mW (commercial)

C2613

Abstract: C2614 c2615 C2611 C2617 7C261 7C264 CY7C261 CY7C263 CY7C264
Contextual Info: CY7C261 CY7C263/CY7C264 8K x 8 Power-Switched and Reprogrammable PROM Features Functional Description The CY7C261, CY7C263, and CY7C264 are high-performance 8192-word by 8-bit CMOS PROMs. When deselected, the 7C261 automatically powers down into a low-power standby mode. It is packaged in a 300-mil-wide package. The 7C263

C2614

Abstract: CY7C264 7C261 7C264 CY7C261 CY7C263 C2612 C2611 C261-4 MIL-STD-1835C-4
Contextual Info: CY7C261 CY7C263/CY7C264 D Features PROMs 20 ns commercial Functional Description 25 ns (military) Low power 660 mW (commercial) 770 mW (military) Super low standby power (7C261) Less than 220 mW when deselected Fast access: 20 ns EPROM technology 100% programĆ

p20d

Abstract: CERPAK data retention eprom Cypress 7c26 CY7C261 CY7C263 CY7C264 CY7C266 CY7C269 EME-6300H
Contextual Info: Qualification Report March, 1992 QTP 91296 Version 1.0 64K EPROM FAMILY, 0.8µ MARKETING PART NUMBER DEVICE DESCRIPTION CY7C261 8K x 8 POWER-SWITCHED CY7C263 8K x 8 CY7C264 8K x 8 600-MIL PKG CY7C266 8K x 8 POWER-SWITCHED EPROM PINOUT CY7C269 8K x 8 REGISTERED DIAGNOSTIC

D2618

Abstract: 3M Touch Systems
Contextual Info: CY7C2644KV18 144-Mbit QDR II+ SRAM Two-Word Burst Architecture 2.0 Cycle Read Latency with ODT 144-Mbit QDR ® II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT Features Configurations Separate independent read and write data ports

Contextual Info: CY7C261 CY7C263/CY7C264 CYPRESS SEMICONDUCTOR • CMOS for optimum speed/power • Windowed for reprogrammability • High speed — 20 ns commercial — 25 ns (military) • Low power — 660 mW (commercial) — 770 mW (military) • Super low standby power (7C261)

AT25080N-10SA-2.7C

Contextual Info: CY7C261 CY7C263/CY7C264 CYPRESS SEMICONDUCTOR Features • CMOS for optimum speed/power • Windowed for reprogrammability • High speed — 20 ns commercial — 25 ns (m ilitai?) • Low power — 660 mW (commercial) — 770 mW (military) • Super low standby power (7C261)

Contextual Info: CY7C261 CY7C263/CY7C264 r^yppircc SEMICONDUCTOR Features TTL-compatible I/O • D irect replacement for bipolar PROMs • CMOS for optimum speed/power • Windowed for reprogrammability Functional Description • High speed — 20 ns comm ercial — 25 ns (military)

7C261

Abstract: 7c264
Contextual Info: CY7C261 CY7C263/CY7C264 WÈP CYPRESS 8K x 8 Power-Switched and Reprogrammable PROM floating-gate technology and byte-wide in­ telligent programming algorithms. The CY7C261, CY7C263, and CY7C264 are plug-in replacements for bipolar de­ vices and offer the advantages of lower

MIL-STD-183

Abstract: 7c264 6135W
Contextual Info: CY7C261 CY7C263/CY7C264 p yp: v « *1 X X 8Kx 8 Power-Switched and Reprogrammable PROM - Features Functional Description • C M O S fo r o ptim u m sp ee d /p o w e r T h e C Y 7 C 2 6 1 , C Y 7C 263, and C Y 7 C 2 64 are high-perform ance 8192-w ord by 8-bit C M O S PRO M s. W hen de selected ,

7C261

Abstract: 7C261-25 C2612 CY7C263-45DC C2613 J-64 CY7C263-35DMB CY7C261 DIODE SMD W12 75 C261
Contextual Info: CYPRESS SEMIC ON DUC TOR MbE D BSfl^bbS □□Qb704 1 n C Y P CY7C261 CY7C263/CY7C264 CYPRESS SEMICONDUCTOR Features 8192 x 8 Power-Switched and Reprogrammable PROM • TTL-compatible I/O • Direct replacement for bipolar PROMs • CMOS for optimum speed/power

7C261

Abstract: 7c264 CY7C261-35WC C2617 cerdip z PACKAGE CY7C263-35DMB CY7C261 CY7C263 CY7C264 7C261-45
Contextual Info: 1 CY7C261 CY7C263/CY7C264 8K x 8 Power-Switched and Reprogrammable PROM Features Functional Description • CMOS for optimum speed/power • Windowed for reprogrammability • High speed — 20 ns commercial The CY7C261, CY7C263, and CY7C264 are high-performance 8192-word by 8-bit CMOS PROMs. When deselected,

CY7C263

Abstract: 7C264 7C261 C261 CY7C261 CY7C264 CY7C263-45WC CY7C264-55 cy7c261-45wmb CY7C264-45WMB
Contextual Info: CY7C261 CY7C263/CY7C264 CYPRESS Features • Capable of withstanding greater than 2001V static discharge • CMOS for optimum speed/power • Windowed for reprogrammability • High speed — 20 ns commercial — 25 ns (military) • Low power — 660 mW (commercial)

3M Touch Systems

Contextual Info: CY7C2644KV18 144-Mbit QDR II+ SRAM Two-Word Burst Architecture 2.0 Cycle Read Latency with ODT 144-Mbit QDR ® II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT Features Configurations Separate independent read and write data ports

CY7C263-55PC

Abstract: CY7C261 CY7C263 CY7C264 7C261 7C264
Contextual Info: 1 CY7C261 CY7C263/CY7C264 8K x 8 Power-Switched and Reprogrammable PROM Features the CY7C261 automatically powers down into a low-power standby mode. It is packaged in a 300-mil-wide package. The CY7C263 and CY7C264 are packaged in 300-mil-wide and 600-mil-wide packages respectively, and do not power down

Contextual Info: CY7C2642KV18/CY7C2644KV18 144-Mbit QDR II+ SRAM Two-Word Burst Architecture 2.0 Cycle Read Latency with ODT 144-Mbit QDR ® II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) with ODT Features • Separate independent read and write data ports

Contextual Info: CY7C2642KV18/CY7C2644KV18 144-Mbit QDR II+ SRAM Two-Word Burst Architecture 2.0 Cycle Read Latency with ODT 144-Mbit QDR ® II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) with ODT Features • Separate independent read and write data ports

7C263-55

Abstract: 7C264 7C261 CY7C261 CY7C263 CY7C264 7C264-45 7c264-35 518-0102
Contextual Info: CY7C261 CY7C263/CY7C264 8K x 8 Power-Switched and Reprogrammable PROM Features Functional Description • CMOS for optimum speed/power • Windowed for reprogrammability • High speed The CY7C261, CY7C263, and CY7C264 are high-performance 8192-word by 8-bit CMOS PROMs. When deselected,

7C264

Abstract: 7C263-45 cy7c261-25wmb 7C261 CY7C261 CY7C263 CY7C264 7C261-25 7C263-55 7C264-45
Contextual Info: CY7C261 CY7C263/CY7C264 8K x 8 Power-Switched and Reprogrammable PROM Features Functional Description • CMOS for optimum speed/power • Windowed for reprogrammability • High speed The CY7C261, CY7C263, and CY7C264 are high-performance 8192-word by 8-bit CMOS PROMs. When deselected,