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D000M54 Datasheets Context Search
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Contextual Info: • S00M200 V96BMC jj ; v D000M54 STO Rev. D HIGH PERFORMANCE BURST DRAM CONTROLLER - FOR i960Cx/Hx/Jx PROCESSORS • Pin/Software compatible with earlier V96BMC. • Integrated Page Cache Management. • Direct interfaces to i960Cx/Hx/Jx processors. • 2Kbyte burst transaction support. |
OCR Scan |
S00M200 V96BMC D000M54 i960Cx/Hx/Jx V96BMC. i960Cx/Hx/Jx 512Mb 24-bit 40MHz 132-pin |