D1P 22 16B Search Results

J239

Abstract: AVDD33 J236 MAX5890 C1005X5R1A104KT LMK105BJ104KV T3/mrc d2n MAX5891 T494A106K010AS TAJB476K006R
Contextual Info: 19-0504; Rev 2; 7/07 MAX5889/MAX5890/MAX5891 Evaluation Kits Features The MAX5889, MAX5890, and MAX5891 evaluation kits EV kits are each fully assembled and tested printedcircuit boards (PCBs) that contain all the components necessary to evaluate the performance of the

Contextual Info: WM8235 w 70MSPS 9-Channel AFE with Sensor Timing Generation and LVDS/CMOS Data Output DESCRIPTION FEATURES The WM8235 is a 16-bit analogue front end/digitiser IC which processes and digitises the analogue output signals from CCD sensors or Contact Image Sensors CIS at pixel

Contextual Info: WM8234 w 70MSPS 6-Channel AFE with Sensor Timing Generation and LVDS/CMOS Data Output DESCRIPTION FEATURES The WM8234 is a 16-bit analogue front end/digitiser IC which processes and digitises the analogue output signals from CCD sensors or Contact Image Sensors CIS at pixel

WM8233

Abstract: OP10 WAN0118 C28E
Contextual Info: WM8233 w 70MSPS 6-Channel AFE with Sensor Timing Generation and LVDS/CMOS Data Output DESCRIPTION FEATURES The WM8233 is a 16-bit analogue front end/digitiser IC which processes and digitises the analogue output signals from CCD sensors or Contact Image Sensors CIS at pixel

J-STD-020B

Abstract: gd2v WM8232 wm823 WAN_0118
Contextual Info: WM8232 w 70MSPS 3-Channel AFE with Sensor Timing Generation and LVDS/CMOS Data Output DESCRIPTION FEATURES The WM8232 is a 16-bit analogue front end/digitiser IC which processes and digitises the analogue output signals from CCD sensors or Contact Image Sensors CIS at pixel

Motorola D8N

Abstract: AD9781BCPZRL7
Contextual Info: Dual 12-/14-/16-Bit, LVDS Interface 600 MSPS DACs AD9780/AD9781/AD9783 Preliminary Technical Data FEATURES GENERAL DESCRIPTION High dynamic range, dual DAC parts Low noise and intermodulation distortion Single carrier WCDMA ACLR = 80 dBc @ 61.44 MHz IF Innovative switching output stage permits useable outputs

AD9780BCPZ

Abstract: BAV99ZXCT AD9783 ADL5370 AVDD33 wcdma baseband 0x0547
Contextual Info: Dual 12-/14-/16-Bit, LVDS Interface 600 MSPS DACs AD9780/AD9781/AD9783 FEATURES GENERAL DESCRIPTION High dynamic range, dual DAC parts Low noise and intermodulation distortion Single carrier W-CDMA ACLR = 80 dBc @ 61.44 MHz IF Innovative switching output stage permits usable outputs

MO-220-VNND-4

Contextual Info: REVISIONS LTR DESCRIPTION DATE Prepared in accordance with ASME Y14.24 APPROVED Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV PAGE 1 2 3 PMIC N/A PREPARED BY Phu H. Nguyen Original date of drawing YY MM DD CHECKED BY 13-01-11 Phu H. Nguyen

Contextual Info: DAC5681 www.ti.com SLLS864 – AUGUST 2007 16-BIT, 1.0 GSPS DIGITAL-TO-ANALOG CONVERTER DAC FEATURES 1 • • • • 16-Bit Digital-to-Analog Converter (DAC) 1.0 GSPS Update Rate 16-Bit, 1.0 GSPS Input LVDS Data Bus – 8 Sample Input FIFO – On-Chip Delay Lock Loop

MO-220-VNND-4

Abstract: adl537x D8P analog devices
Contextual Info: Dual, 16-Bit, 1130 MSPS, TxDAC+ Digital-to-Analog Converter AD9122-EP Enhanced Product FEATURES GENERAL DESCRIPTION Flexible LVDS interface allows word, byte, or nibble load Single-carrier W-CDMA ACLR = 82 dBc at 122.88 MHz IF Analog output: adjustable 8.7 mA to 31.7 mA

comcode

Abstract: GR-253 TRCV012G5 TRCV012G7 TTRN012G5 TTRN012G7
Contextual Info: Preliminary Data Sheet August 2000 TTRN012G5 2.5 Gbits/s and TTRN012G7 (2.5 Gbits/s and 2.7 Gbits/s) Clock Synthesizer, 16:1 Data Multiplexer Features • TTRN012G5 supports OC-48/STM-16 data rate ■ TTRN012G7 supports: — OC-48/STM-16 data rate — RS (255, 239) forward error correction (FEC)

PR79A

Abstract: PR65A PR83a PR88A PR97A PR74A pr41a PR50A ASP-122953-01 PR91A
Contextual Info:  LatticeECP3 I/O Protocol Board to Texas Instruments ADC/DAC Adapter Board User’s Guide May 2010 Revision: EB54_01.2  Lattice Semiconductor LatticeECP3 I/O Protocol Board to Texas Instruments ADC/DAC Adapter Board User’s Guide Introduction The LatticeECP3 I/O Protocol Board to TI ADC/DAC Adapter provides a convenient platform to evaluate, test

GR-253

Abstract: TRCV012G5 TTRN012G5
Contextual Info: Advance Data Sheet September 1999 TTRN012G5 2.5 GHz Clock Synthesizer, 16:1 Data Multiplexer Features • Fully integrated 2.5 GHz clock synthesizer; 16:1 data multiplexer; supports OC-48/STM-16 data rates ■ Supports clockless data transfer into the 16:1

GR-253

Abstract: TRCV012G5 TRCV012G7 TTRN012G5 TTRN012G7 D12N cdm 12.6 laser
Contextual Info: Advance Data Sheet March 2000 TTRN012G5 2.5 Gbits/s and TTRN012G7 (2.5 Gbits/s and 2.7 Gbits/s) Clock Synthesizer, 16:1 Data Multiplexer Features • TTRN012G5 supports OC-48/STM-16 data rate ■ TTRN012G7 supports: — OC-48/STM-16 data rate — RS (255, 239) forward error correction (FEC)

TRCV012G5

Abstract: TTRN012G5 GR-253 BELLCORE AST3
Contextual Info: Advance Data Sheet September 1999 TRCV012G5 2.5 Gbits/s Limiting Amplifier, Clock Recovery, 1:16 Data Demultiplexer Features • Fully integrated limiting amplifier, clock recovery, 1:16 data demultiplexer ■ Supports OC-48/STM-16 data rates ■ 2.5 Gbits/s data output and 2.5 GHz recovered

Contextual Info: User's Guide SLAU236A – November 2007 – Revised October 2008 DAC5681/81z/82z EVM 1 2 3 4 5 6 7 Contents Overview . 3 1.1 Purpose . 3

GR-253

Abstract: TRCV012G5 TRCV012G7 TTRN012G5 TTRN012G7 ast0
Contextual Info: Advance Data Sheet February 2000 TRCV012G5 2.5 Gbits/s and TRCV012G7 2.7 Gbits/s Limiting Amplifier, Clock Recovery, 1:16 Data Demultiplexer Features • TRCV012G5 supports OC-48/STM-16 data rate ■ TRCV012G7 supports: — OC-48/STM-16 data rate — RS 255, 239 forward error correction (FEC)

GR-253

Abstract: TTRN0110G
Contextual Info: Data Sheet March 29, 2002 TTRN0110G 10 Gbits/s Clock Synthesizer, 16:1 Data Multiplexer Features Applications Supports standard OC-192/STM-64 data rate of 9.95328 Gbits/s up through forward error correction FEC rate of 10.7092 Gbits/s as well as the Ethernet rate of 10.3125 Gbits/s

234h

Abstract: GR-253 TRCV012G5 TRCV012G7 TTRN012G5 TTRN012G7
Contextual Info: Preliminary Data Sheet August 2000 TRCV012G5 2.5 Gbits/s and TRCV012G7 (2.5 Gbits/s and 2.7 Gbits/s) Limiting Amplifier, Clock Recovery, 1:16 Data Demultiplexer Features • TRCV012G5 supports OC-48/STM-16 data rate ■ TRCV012G7 supports: — OC-48/STM-16 data rate

Contextual Info: DAC5681 www.ti.com SLLS864 – AUGUST 2007 16-BIT, 1.0 GSPS DIGITAL-TO-ANALOG CONVERTER DAC FEATURES 1 • • • • 16-Bit Digital-to-Analog Converter (DAC) 1.0 GSPS Update Rate 16-Bit, 1.0 GSPS Input LVDS Data Bus – 8 Sample Input FIFO – On-Chip Delay Lock Loop

AVDD33

Abstract: D12N D13N MAX5889 MAX5890 MAX5891 MAX5891EVKIT
Contextual Info: KIT ATION EVALU LE B A IL A AV 19-3619; Rev 0; 4/05 14-Bit, 600Msps, High-Dynamic-Performance DAC with LVDS Inputs The MAX5890 advanced 14-bit, 600Msps, digital-toanalog converter DAC meets the demanding performance requirements of signal synthesis applications

Contextual Info: KIT ATION EVALU LE B A IL A AV 19-3542; Rev 4; 2/07 16-Bit, 600Msps, High-Dynamic-Performance DAC with LVDS Inputs The MAX5891 advanced 16-bit, 600Msps, digital-toanalog converter DAC meets the demanding performance requirements of signal synthesis applications

MAX5889

Abstract: MAX5890 MAX5891 MAX5891EGK MAX5891EVKIT
Contextual Info: KIT ATION EVALU LE B A IL A AV 19-3542; Rev 0; 2/05 16-Bit, 600Msps, High-Dynamic-Performance DAC with LVDS Inputs The MAX5891 advanced 16-bit, 600Msps, digital-toanalog converter DAC meets the demanding performance requirements of signal synthesis applications

Contextual Info: DAC5681Z www.ti.com SLLS865 – AUGUST 2007 16-BIT, 1.0 GSPS 2x-4x INTERPOLATING DIGITAL-TO-ANALOG CONVERTER DAC DESCRIPTION • • • • • • • • • 16-Bit Digital-to-Analog Converter (DAC) 1.0 GSPS Update Rate 16-Bit, 1.0 GSPS Input LVDS Data Bus