DDD1Q13 Search Results

M8254

Contextual Info: M'îE » • SöbAMSb rillll MA T R A □QDD^74Tb4 mW mmÊÊÊ ¿ W H S <- November 1990 M H S M8254 DATA SHEET PROGRAMMABLE INTERVAL TIM ER FEATURES I THREE INDEPENDENT 16-BIT COUNTERS . STATUS READ-BACK COMMAND . SIX PROGRAMMABLE COUNTER MODES (IN­ TERRUPT ON TERMINAL COUNT, HARDWARE

8085 pin diagram

Contextual Info: J> SöböMSb m n ilII I W MATRA m GQGGTTS bll Novem ber 1990 M H S M8259 DATA SHEET_ PROGRAMMABLE INTERRUPT CONTROLLER FEATURES . 8085,8086,8088 COMPATIBLE . EIGHT-LEVEL PRIORITY CONTROLLER . EXPANDABLE TO 64 LEVELS . PROGRAMMABLE INTERRUPT MODES FULLY

Contextual Info: SfibôHSb DDDGTTfl OGT • T -1 S -3 7 -0 5 MMHS November 1990 MAT RA M H S M6402 MACROCELL DATA SHEET UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER FEATURES OPERATION GUARANTEED FROM D.C. TO 8.0 MHz LOW POWER CMOS DESIGN PROGRAMMABLE WORD LENGHT, STOPS BITS

s3 tech

Contextual Info: T> m S ö b ß M S b Q O D O m = .= — — m n llll i m MATRA « S3? • M M H S _ =r— ¡ r ^ , °n l Novem ber 1990 M H S MI2C DATA SHEET_ I2C PROTOCOL CONTROLLER FEATURES . FU LL I2C C O M PATIBLE . UP TO 100 K BITS/S T R A N SF E R RATE C A P A ­

M8251A

Contextual Info: 4RE ]> • SöböHSt. DOGOTbö n llll I y T HATRA M IbD ■ MJ1HSp75- 3 7 ' November 1990 M H S M8251A DATA SHEET UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER FEATURES . . ASYNCHRONOUS RECEIVER/TRANSMITTER ASYNCHRONOUS 5 -8 BIT CHARACTERS ; CLOCK RATE — 16 OR 64 TIMES BAUD RATE ;