DEMULTIPLEXER Search Results

54HC154

Contextual Info: SN54HC154, SN74HC154 LINE TO 16 LINE DECODERS/DEMULTIPLEXERS D 2 6 8 4 , DECEMBER 1 9 8 2 -R E V IS E D SEPTEMBER 1987 • Decodes 4 Binary-Coded Inputs into One of 16 Mutually Exclusive Outputs • Performs the Demultiplexing Function by Distributing Data From One Input to Any

Contextual Info: SN74CBT3257 QUADRUPLE 2-BIT TO 1-BIT FET MULTIPLEXER/DEMULTIPLEXER SCDS017-MAY 1995 I • • • • S[ 1 1B1 [ 2 1B2 [ 3 1A [ 4 description The SN74CBT3257 is a quadruple 2-bit to 1-bit high-speed TTL-compatible FET multiplexer/ demultiplexer. The low on-state resistance of the

Contextual Info: SN74LVC137 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER WITH ADDRESS LATCHES SCAS340 - MARCH 1994 » EPIC Enhanced-Performance Implanted CMOS Submicron Process • Typical V o lp (Output Ground Bounce) D, DB, OR PW PACKAGE (TOP VIEW) A[ B[ c[ Ü2A [ S2B[ G1[

Contextual Info: UT54ACS 139/UT54ACTS 139 Radiation-Hardened Dual 2-Line to 4-Line Decoders/Demultiplexers PINOUTS FEATURES 16-Pin DIP Top View • Incorporates two enable inputs to simplify cascading and/or data reception • 1.2 1 radiation-hardened CMOS - Latchup immune

051b

Contextual Info: SN54F138, SN74F138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SDFS051B - MARCH 1987 - REVISED JULY 1996 Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems SN54F13 8 . . . J PACKAGE SN74F138. . . D OR N PACKAGE TOP VIEW u Incorporates Three Enable Inputs to

D3318

Contextual Info: 74AC11139 DUAL 2-LINE TO 4-LINE DECODER/DEMULTIPLEXER D3318, JULY 1989 - R EV ISED APRIL 1993 * Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems * Incorporates Two Enable Inputs to Simplify Cascading and/or Data Reception

Contextual Info: SN74ALS137, SN74AS137, SN54ALS137 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS WITH ADDRESS LATCHES D2661, APRIL 1982 - REVISED M AY 1986 Combings Decoder and 3-Bit Addreis Latch SN54ALS137 . . . J PACKAGE SN74ALS137, SN74AS137 . . . D O R N PACKAGE Incorporates 2 Output Enables to Simplify

LS138

Abstract: SN54ALS138
Contextual Info: TYPES SN54ALS138, SN54AS138, SN74ALS138, SN74AS138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS D 2 6 6 1 , APRIL 1 9 8 2 — REVISED DECEMBER 1 9 8 3 Designed Specifically for High-Speed Mem ory Decoders and Data Transmission Systems SN 54A LS138, SN 54A S 138 .

74F139 equivalent

Contextual Info: TOSHIBA TC74ACT139 2-to-4 Line Decoder Features: • The TC74ACT139 is an advanced high speed CMOS 2-TO-4 LINE DECODER/DEMULTIPLEXER fabricated with silicon gate and double-layer metal wiring C2MOS technology. It achieves the high speed operation similar to equivalent

SN74F138

Contextual Info: SN54F138, SN74F138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SDFS051 A - D2932, MARCH 1987 - REVISED OCTOBER 1993 Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems Incorporates Three Enable Inputs to Simplify Cascading and/or Data Reception

cd4051a

Abstract: TP4053 TP4051 TP4052 TRTE CD4052A KSL 2101
Contextual Info: f TYPES TF4051A, TF4052A, TF4053A. TP4051A, TP4052A, TP4053A ANALOG MULTIPLEXERS/DEMULTIPLEXERS I CMOS LOGIC CIRCU ITS S E P 7 fc M « L H 1 9 7 ‘j Desired to be Interchangeable with RCA CD4051A, CD4052A, and CD4053A Difference in ron Between Switches in One Package Typically 5 12 at

SN54ALS137

Contextual Info: SN74ALS137, SN74AS137, SN54ALS137 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS WITH ADDRESS LATCHES D2661, APRIL 1982 - REVISED MAY 1986 Combines Decoder and 3-Bit Address Latch Incorporates 2 Output Enables to Simplify Cascading SN54ALS137 . . . J PACKAGE SN74ALS137, SN74AS137 . . . D OR N PACKAGE

042b

Contextual Info: 74AC11138 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER SCAS042B - MAY 1988 - REVISED A P R IL I 996 D, N, OR PW PACKAGE TOP VIEW Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems Y1 [ 1 Y2 [ 2 Incorporates Three Enable Inputs to

Contextual Info: SN54LV138, SN74LV138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SC LS190P- FEBRUARY 19 9 3 - REVISED JULY 1996 EPIC Enhanced-Performance Implanted CMOS 2-fi Process Typical Vqlp (Output Ground Bounce) < 0.8 V at Vc c , Ta = 25°C SN54LV138. . . J OR W PACKAGE

74HC239

Abstract: C-239 SN74HC239
Contextual Info: SN54HC239, SN74HC239 DUAL 2-LINE TO 4 LINE DECODERS/DEMULTIPLEXERS D 2 8 0 4 . MARCH 1 9 8 4 -R E V IS E D SEPTEMBER 1987 • • S N 5 4 H C 2 3 9 . . . J P AC KAG E S N 7 4 H C 2 3 9 . . . D W OR N P A C K A G E TO P V IE W ! IG C 1 U 1A C 2 Incorporates 2 Enable Inputs to Simplify

Contextual Info: SN74ALS156 DUAL 2-LINE TO 4-LINE DECODER/DEMULTIPLEXER WITH OPEN-COLLECTOR OUTPUTS D 2 9 3 0 , JU N E 1 9 8 6 D OR N PACKAGE Applications: Dual 2-Line to 4-Line Decoder Dual 1-Line to 4-Line Demultiplexer 3-Line to 8-Line Decoder 1-Line to 8-Line Demultiplexer

Contextual Info: 74ACT11139 DUAL M IN E TO 4-LINE DECODER/DEMULTIPLEXER SCASI 75 - D3907, SEPTEMBER 1991 - REVISED APRIL 1993 D, N, OR PW PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems

Contextual Info: SN54AHC138, SN74AHC138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS S CLS258C - DECEM BER 1995 - REVISED JULY 1996 Operating Range 2-V to 5.5-V Vqc E P IC * Enhanced-Performance Implanted CMOS Process SN54AMC138 . . . J O R W PACKAGE SN74AHC138 . . . D, DB, N, OR PW PACKAGE

Contextual Info: SN54HC139, SN74HC139 DUAL 2 LINE TO 4-LINE DECODERS/DEMULTIPLEXERS D 2 6 8 4 , DECEMBER 1 9 8 2 -R E V IS E D SEPTEMBER 1987 D esigned S pecifically for H igh-Speed S N 5 4 H C 1 3 9 . . . J PACKAGE S N 7 4 H C 1 3 9 . . . O W OR N PACKAGE M e m o ry D ecoders and D ata Transm ission

4052BP

Abstract: 5v 10rj TC4052BP TC4052 TC4051BP
Contextual Info: • TC4051BP/BF, TC4052BP/BF, ■ TC4053BP/BF TC4051BP/TC4051BF SINGLE 8-CHANNEL MULTIPLEXER/DEMULTIPLEXER TC4052BP/TC4052BF DIFFERENTIAL 4-CHANNEL MULTIPLEXER/DEMULTIPLEXER TC4053BP/TC4053BF TRIPLE 2-CHANNEL MULTIPLEXER/DEMULTIPLEXER TC4051BP/BF, TC405 2 B P / B F and TC405 3 B P / B F are

Contextual Info: SN54HCT237, SN74HCT237 3 LINE TO 8-LINE DECODERS/DEMULTIPLEXERS WITH ADDRESS LATCHES D 2 8 0 4 , M A R C H 1 9 8 4 - R E V I S E D JU N E 1 9 8 9 • Inputs are TTL-Voltage Compatible S N 5 4 H C T2 3 7 . . . J PA C KA G E SN 74H C T237 . . . N PACKAG E •

Contextual Info: SN54ALS138A, SN54AS138, SN74ALS138A, SN74AS138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SDAS055E – APRIL 1982 – REVISED JULY 1996 D D D Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems Incorporate Three Enable Inputs to Simplify

Contextual Info: SN54AHCT139, SN74AHCT139 DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS SCLS267J – DECEMBER 1995 – REVISED NOVEMBER 1999 D D D D description SN54AHCT139 . . . J OR W PACKAGE SN74AHCT139 . . . D, DB, DGV, N, OR PW PACKAGE TOP VIEW 1G 1A 1B 1Y0 1Y1 1Y2

sn74als138a ti

Abstract: SN54ALS138
Contextual Info: SN54ALS138A, SN54AS138, SN74ALS138A, SN74AS138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SDAS055E – APRIL 1982 – REVISED JULY 1996 D D D Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems Incorporate Three Enable Inputs to Simplify