DIFFERENCE BETWEEN OC48 OC192 Search Results

PM5326

Abstract: PM5377 STS192 STS-48
Contextual Info: PM5377 TSE 240 Released Single Chip 96-Port STS-1/STM-0 Cross-Connect FEATURES DELAY MANAGEMENT • Implements a 240G memory switch fabric with STS-1/AU-3 switching granularity. • 96 ingress and 96 egress STS48/STS-12 ports for a maximum of 4608 STS-1/AU-3 streams in a single

Contextual Info: PM5308 TSE 120 Released AM Single Chip 74-Port STS-1/STM-0 Cross-Connect TOH PROCESSING AND TESTING rtm LB_IFP[4:1] 51 4: LB_EFP[4:1] LBTE x4 of Pa LB_ECLK[4:1] m R_P/N [1.25] R_P/N [26] R_P/N [27.74] RASIO 3G Rx ESSI Rx RASIO 3G Rx ESSI Rx RASIO 3G Rx

PM5326

Abstract: PM5369 TUPP 9953 STM64 STS-192 STS-48 difference between oc48 oc192 PMC DM 100 108byte PM5308
Contextual Info: PM5308 TSE 120 Released AM Single Chip 74-Port STS-1/STM-0 Cross-Connect SWITCH PORT CONFIGURATION TOH PROCESSING AND TESTING LB_ID[4:1][1:0] ico R_P/N [26] ESSI Rx RASIO 3G Rx ESSI Rx RASIO 3G Rx ESSI Rx 52 DMI DMO Memory Switch Core ESSI Tx RASIO 3G Tx ESSI Tx

Contextual Info: PM5308 TSE 120 Released PM Single Chip 74-Port STS-1/STM-0 Cross-Connect LB_IFP[4:1] rtm LBTE x4 R_P/N [26] R_P/N [27.74] LB_ECLK[4:1] RASIO 3G Rx ESSI Rx RASIO 3G Rx ESSI Rx RASIO 3G Rx ESSI Rx DMI ESSI Tx RASIO 3G Tx ESSI Tx RASIO 3G Tx ESSI Tx RASIO

OC-192/STM-64

Contextual Info: PM5308 TSE 120 Released PM Single Chip 74-Port STS-1/STM-0 Cross-Connect SWITCH PORT CONFIGURATION co LB_IFP[4:1] n LB_ID[4:1][1:0] 17 7: :0 Th BLOCK DIAGRAM LB_ED[4:1][1:0] LBTO x4 LB_EFP[4:1] LBTE (x4) LB_ICLK[4:1] er In LB_ECLK[4:1] R_P/N [26] R_P/N [27.74]

Contextual Info: PM5308 TSE 120 Released AM Single Chip 74-Port STS-1/STM-0 Cross-Connect SWITCH PORT CONFIGURATION LB_ID[4:1][1:0] 37 5: :3 LB_ED[4:1][1:0] LBTO x4 LB_EFP[4:1] LBTE (x4) LB_ECLK[4:1] rtm in LB_ICLK[4:1] er LB_IFP[4:1] of Pa R_P/N [1.25] R_P/N [26] m ea

Contextual Info: PM5308 TSE 120 Released PM Single Chip 74-Port STS-1/STM-0 Cross-Connect TOH PROCESSING AND TESTING co LB_IFP[4:1] of 13 1: :4 LBTO x4 LB_EFP[4:1] LBTE (x4) LB_ICLK[4:1] er In LB_ECLK[4:1] tm in R_P/N [1.25] R_P/N [26] R_P/N [27.74] RASIO 3G Rx ESSI Rx

VSC9186

Abstract: GR-253-CORE STM-16 STM-64 STS-192 STM64
Contextual Info: TIMESTREAMTM PRODUCT FAMILY VSC9186 VSC9186 Killington - Quad STS-48/STM-16 and STS-192/STM-64 Line Interface S P E C I F I C AT I O N S : 2.5V I/O and 1.8V Core Power Supplies 0.18µ CMOS Technology 720-pin CCGA /1.0mm Column Pitch 10W Maximum Power Consumption

STM-64

Abstract: GR-253-CORE STM-16 VSC9186 STM64
Contextual Info: PHYSICAL LAYER PRODUCT TIMESTREAM PRODUCT FAMILY VSC9186 VSC9186 Killington - Quad STS-48/STM-16 and STS-192/STM-64 Line Interface S P E C I F I C AT I O N S : 42.5V I/O and 1.8V Core Power Supplies 40.18µ CMOS Technology 4720-pin CCGA /1.0mm Column Pitch

Contextual Info: Agilent 71501D Jitter Analysis System Product Overview A flexible, wide bandwidth jitter analysis system analyzer1, SDH/SONET standard tests for jitter transfer, jitter tolerance, and jitter generation/output can be performed at STM-4/OC-12 622 Mb/s , STM-16/OC-48

Lucent Technologies fiber optics cable

Abstract: LUCENT TECHNOLOGIES CAT-5 LAN lucent wdm SWITCH L3 lucent optical switch wireless lan 10 KM Lucent Technologies single mode fiber
Contextual Info: Gigabit Ethernet in the LAN and MAN Doug Ruby Vice President and CTO Internetworking Systems - Enterprise Agenda q Why all the fuss? q Trends q LAN -MAN design trends – What is in the LAN/MAN backbone today? q Why gigabit WAN? q Current alternatives q Future options

83732A

Contextual Info: Agilent 71501C Jitter Analysis System Product Overview A flexible, wide bandwidth jitter analysis system ation/output can be performed at STM-4/OC-12 622 Mb/s , and STM-16/OC-48 (2488 Mb/s)3 rates. Because the system is completely frequency agile, these tests can also be performed at

Contextual Info: ZL30414 SONET/SDH Clock Multiplier PLL Data Sheet Features • February 2005 Meets jitter requirements of Telcordia GR-253CORE for OC-192, OC-48, OC-12, and OC-3 rates • Meets jitter requirements of ITU-T G.813 for STM64, STM-16, STM-4 and STM-1 rates •

Contextual Info: ZL30414 SONET/SDH Clock Multiplier PLL Data Sheet Features • June 2006 Meets jitter requirements of Telcordia GR-253CORE for OC-192, OC-48, OC-12, and OC-3 rates • Meets jitter requirements of ITU-T G.813 for STM64, STM-16, STM-4 and STM-1 rates • Provides four LVPECL differential output clocks at

OSCILLATOR, TCXO, 16.384 MHZ

Abstract: ZL30414 ZL30414QGC GR-253-CORE STM-16 STM64 STM-64
Contextual Info: ZL30414 SONET/SDH Clock Multiplier PLL Data Sheet Features June 2004 • Meets jitter requirements of Telcordia GR-253CORE for OC-192, OC-48, OC-12, and OC-3 rates • Meets jitter requirements of ITU-T G.813 for STM64, STM-16, STM-4 and STM-1 rates • Provides four LVPECL differential output clocks at

Contextual Info: ZL30414 SONET/SDH Clock Multiplier PLL Data Sheet Features • June 2006 Meets jitter requirements of Telcordia GR-253CORE for OC-192, OC-48, OC-12, and OC-3 rates • Meets jitter requirements of ITU-T G.813 for STM64, STM-16, STM-4 and STM-1 rates • Provides four LVPECL differential output clocks at

c622

Abstract: GR-253-CORE STM-16 STM64 STM-64 ZL30414 ZL30414QGC
Contextual Info: ZL30414 SONET/SDH Clock Multiplier PLL Data Sheet Features July 2003 • Meets jitter requirements of Telcordia GR-253CORE for OC-192, OC-48, OC-12, and OC-3 rates • Meets jitter requirements of ITU-T G.813 for STM64, STM-16, STM-4 and STM-1 rates • Provides four LVPECL differential output clocks at

GR-253-CORE

Abstract: STM-16 STM64 ZL30414 ZL30414QGC ZL30414QGC1 trf 640
Contextual Info: ZL30414 SONET/SDH Clock Multiplier PLL Data Sheet Features • February 2005 Meets jitter requirements of Telcordia GR-253CORE for OC-192, OC-48, OC-12, and OC-3 rates • Meets jitter requirements of ITU-T G.813 for STM64, STM-16, STM-4 and STM-1 rates •

GR-253-CORE

Abstract: STM-16 STM64 ZL30414 ZL30414QGC
Contextual Info: ZL30414 SONET/SDH Clock Multiplier PLL Data Sheet Features • June 2006 Meets jitter requirements of Telcordia GR-253CORE for OC-192, OC-48, OC-12, and OC-3 rates • Meets jitter requirements of ITU-T G.813 for STM64, STM-16, STM-4 and STM-1 rates • Provides four LVPECL differential output clocks at

kcf 201

Contextual Info: ZL30414 SONET/SDH Clock Multiplier PLL Data Sheet Features • July 2011 Meets jitter requirements of Telcordia GR-253CORE for OC-192, OC-48, OC-12, and OC-3 rates • Meets jitter requirements of ITU-T G.813 for STM64, STM-16, STM-4 and STM-1 rates • Provides four LVPECL differential output clocks at

Nortel Networks TN16XE

Abstract: TN-16X TN16XE tn16x Nortel OC-48 TransportNode TN-64X preside sdh nortel tn4xe TN64X tn1c
Contextual Info: Product Brief Nortel Networks Preside Solutions for Optical Networks interWAN Applications Helping service providers efficiently manage the new optical network, allowing for the rapid creation, deployment, and delivery of revenue-generating services. Understanding the challenge

GR-253-CORE

Abstract: STM-16 STM64 STM-64 ZL30414 ZL30414QGC
Contextual Info: ZL30414 SONET/SDH Clock Multiplier PLL Data Sheet Features July 2003 • Meets jitter requirements of Telcordia GR-253CORE for OC-192, OC-48, OC-12, and OC-3 rates • Meets jitter requirements of ITU-T G.813 for STM64, STM-16, STM-4 and STM-1 rates • Provides four LVPECL differential output clocks at

Contextual Info: ZL30414 SONET/SDH Clock Multiplier PLL Data Sheet Features July 2003 • Meets jitter requirements of Telcordia GR-253CORE for OC-192, OC-48, OC-12, and OC-3 rates • Meets jitter requirements of ITU-T G.813 for STM64, STM-16, STM-4 and STM-1 rates • Provides four LVPECL differential output clocks at

iball

Abstract: transistor oc 76 GR-253-CORE OC48 STM16 STM-64 ZL30416 ZL30416GGG
Contextual Info: ZL30416 SONET/SDH Clock Multiplier PLL Data Sheet Features June 2004 • Low jitter clock outputs suitable for OC-192, OC48, OC-12, OC-3 and OC-1 SONET applications as defined in Telcordia GR-253-CORE • Low jitter clock outputs suitable for STM-64, STM16, STM-4 and STM-1 applications as defined in