DIN07 Search Results

2D202

Abstract: RCC700A diode D284 D313 Pin diagram
Contextual Info: www.fairchildsemi.com RCC700A Fibre Channel Transceiver 240 to 330 Megabaud Features • • • • • • • • • • • • PECL compatible serial data inputs/outputs • Available in 64-pin PQFP, 68 pin PLCC 240 to 330 Megabaud data rates Compliant with Fibre Channel standard

Contextual Info: H A RR IS S E M I C O N D SE CT OR ’ ••'E: d 4305271 D 0 m i4M0 4 H S P 43481 HARRIS PRELIMINARY Digital Filter January 1989 Features Description • Four Filter Cells The HSP43481 is a video-speed Digital Filter DF designed to efficiently implement vector operations such as

IC 7585 adjust

Abstract: correlator HSP45256
Contextual Info: Cascading Multiple HSP45256 Correlators TM Technical Brief itle 30 bt asing ltiP45 6 rreors utho eyrds terrpoion, ictor) er ) OCI O frk May 1998 When multiple correlators are cascaded for longer reference data sets, the Programmable Delay is used to adjust the timing between chips so that they can be connected with no

Contextual Info: 2 HARRIS Ja n u a ry 1991 Features • Single Chip 3x3 Kernel Convolution • Programmable O n-chip Row Buffers • DC to 32 MHz Clock Rate • Cascadable for Larger Kernels and Images • O n-Chip 8-B it ALU • Dual Coefficient Mask Registers, Switchable in a

HSP48908

Abstract: HSP48908GC-20 HSP48908GC-32 HSP48908JC-20 HSP48908JC-32 HSP48908VC-20 HSP48908VC-32
Contextual Info: HSP48908 TM Data Sheet May 1999 FN2456.5 Two Dimensional Convolver Features The Intersil HSP48908 is a high speed Two Dimensional Convolver which provides a single chip implementation of a video data rate 3 x 3 kernel convolution on two dimensional data. It eliminates the need for external data storage through

45256

Abstract: correlator HARRIS HSP45256 harris 1028
Contextual Info: Harris Semiconductor No. TB306 Harris Digital Signal Processing January 1994 CASCADING MULTIPLE HSP45256 CORRELATORS When multiple correlators are cascaded for longer reference data sets, the Programmable Delay is used to adjust the timing between chips so that they can be connected with no

Contextual Info: HSP45256 HARRIS S E M I C O N D U C T O R Binary Correlator January 1994 Features Description • Reconfigurable 256 Stage Binary Correlator The Harris HSP45256 is a high-speed, 256 tap binary correlator. It can be configured to perform one- or twodimensional correlations of selectable data precision and

32C05

Abstract: HSP45256 HSP45256GC-25 HSP45256GC-33 HSP45256JC-25 HSP45256JC-33 HSP45256JI-25 HSP45256JI-33 CO6R
Contextual Info: HSP45256 Data Sheet May 1999 File Number Binary Correlator Features The Intersil HSP45256 is a high-speed, 256 tap binary correlator. It can be configured to perform one-dimensional or two-dimensional correlations of selectable data precision and length. Multiple HSP45256’s can be cascaded for

HSP48908

Abstract: HSP48908GC-20 HSP48908GC-32 HSP48908JC-20 HSP48908JC-32 HSP48908VC-20 HSP48908VC-32
Contextual Info: HSP48908 Data Sheet May 1999 File Number Two Dimensional Convolver Features The Intersil HSP48908 is a high speed Two Dimensional Convolver which provides a single chip implementation of a video data rate 3 x 3 kernel convolution on two dimensional data. It eliminates the need for external data storage through

MSM66587 Family

Abstract: rl66 MSM66587 CL665S 0200H-09FFH M6658
Contextual Info: ¡ MSM66587 Family User's Manual CMOS 16-bit microcontroller SECOND EDITION ISSUE DATE: Jan. 2000 FEUL66587-02 E2Y0002-2X-13 NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information

Contextual Info: >MCC DEVICE SPECIFICATION Q U A D S E R IA L B A C K P L A N E DEVICE GENERAL DESCRIPTION FEATURES • Broad operating rate range 1.0-1.33 GHz - 1062 MHz (Fibre Channel) - 1250 MHz (Gigabit Ethernet) line rates - 1/2 Rate Operation • Quad Transmitter with phase-locked loop (PLL)

chn7

Contextual Info: HSP45256/883 S HftiSSÄ Binary Correlator January 1994 Features Description • T h is Circuit is Processed in Accordance to M IL-STD883 and is Fully C onform ant Under the Provisions of Paragraph 1.2.1. The Harris H SP45256 is a high-speed, 256 tap binary

32C05

Abstract: CAS IE 116 weighting systems HSP45256 HSP45256GC-25 HSP45256GC-33 HSP45256JC-25 HSP45256JC-33 HSP45256JI-25 HSP45256JI-33
Contextual Info: HSP45256 TM Data Sheet May 1999 FN2814.4 Binary Correlator Features The Intersil HSP45256 is a high-speed, 256 tap binary correlator. It can be configured to perform one-dimensional or two-dimensional correlations of selectable data precision and length. Multiple HSP45256’s can be cascaded for

HSP45256

Contextual Info: HSP45256/883 Binary Correlator February 1998 Features Description • This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. The Intersil HSP45256/883 is a high-speed, 256 tap binary correlator. It can be configured to perform one-dimensional

Contextual Info: 4 3 D2 E7 1 G0S 3 25 7 315 « H A S Two Dimensional Convolver January 1994 Features Description • Single Chip 3 x 3 Kernel Convolution The Harris HSP48908 is a high speed Two Dimensional Convolver which provides a single chip implementation of a video data rate 3 x 3 kernel convolution on two dimensional

DF1 Pinout

Abstract: HSP43891 HSP43891GC-20 HSP43891GC-25 HSP43891GC-30 HSP43891JC-20 HSP43891JC-25 HSP43891JC-30 HSP43891VC-20 HSP43891VC-25
Contextual Info: HSP43891 S E M I C O N D U C T O R Digital Filter January 1996 Features Description • • • • • • • The HSP43891 is a video-speed Digital Filter DF designed to efficiently implement vector operations such as FIR digital filters. It is comprised of eight filter cells

Contextual Info: H A R R HSP48908 I S S E M I C O N D U C T O R Two Dimensional Convolver January 1994 Features Description • Single Chip 3 x 3 Kernel Convolution The Harris HSP48908 is a high speed Two Dimensional Convolver which provides a single chip implementation of a

Contextual Info: S U H U S E M I C O N D U C T O R U A R R HSP48908 I S Two Dimensional Convolver January 1994 Features Description • Single Chip 3 x 3 Kernel Convolution The Harris HSP48908 is a high speed Two Dimensional Convolver which provides a single chip implementation of a

programmable delay

Abstract: 45256 HSP45256
Contextual Info: Cascading Multiple HSP45256 Correlators Technical Brief May 1998 cascaded together; in this example, each is configured as 1x256. In the interest of clarity, the only portions shown are the final stage of the first correlator and the first stage of the second one. The data sample number at each stage for a

DIN-01

Abstract: 802.3z defined DIN00
Contextual Info: Twelve-Channel 2.5G Working Group Phase 1 Specification February 8, 2001 Twelve-Channel 2.5G Working Group Phase 1 Specification – 12xPFM This document, a multi-source agreement developed by Agilent Technologies, W. L. Gore & Associates, and Mitel Semiconductor, provides a common specification for twelve-channel parallel fiber optic transmitters and receivers

Contextual Info: EB HSP45256/883 Binary Correlator February 1992 Description Features • This Circuit is Processed in Accordance to Mil-Std883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. • Reconfigurable 256 Stage Binary Correlator • 1-Bit Reference x 1, 2, 4, or 8-Bit Data

AF3 din 74

Abstract: 212 15 g18 PQFP-128 datasheet VANTIS A10 bga Octal Latches open collector AC25 AF23 IOB80 M275
Contextual Info: PRELIMINARY VF1 FPGA Family FEATURES AND BENEFITS ◆ The industry’s first Variable-Grain-Architecture enables high-density, high-performance ◆ ◆ ◆ ◆ Publication# VF1003-DS-1 Amendment/0 Issue Date: November 1998 VF1 FPGA Family ◆ designs for a wide range of applications

DCM01

Abstract: X20-X21 SUM2016 HSP43881 HSP43881GC-20 HSP43881GC-25 HSP43881GC-30 HSP43881JC-20 HSP43881JC-25 HSP43881JC-30
Contextual Info: HSP43881 TM Data Sheet May 1999 Digital Filter Features The HSP43881 is a video speed Digital Filter DF designed to efficiently implement vector operations such as FIR digital filters. It is comprised of eight filter cells cascaded internally and a shift and add output stage, all in a single integrated

HSP45256

Abstract: G85.A Package F7E3
Contextual Info: HSP45256/883 TM December 1999 Features T UCT ODUC PROD IL TE P R E E T L U O OB S BSTIT T ER S LE SU ns 1-888-IN IB S S PO l.com atio FOR A tral Applic pp@intersi en ta call C email: cen or Description • This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of