DIVIDER BY TWO Search Results

ICS673-01

Abstract: ICS674-01
Contextual Info: DATASHEET ICS674-01 USER CONFIGURABLE DIVIDER Description Features The ICS674-01 consists of two separate configurable dividers. The A Divider is a 7-bit divider and can divide by 3 to 129. The B Divider consists of a 9-bit divider followed by a post divider. The 9-bit divider can divide by 12 to 519. The

ICS674-01

Abstract: ICS673-01
Contextual Info: DATASHEET ICS674-01 USER CONFIGURABLE DIVIDER Description Features The ICS674-01 consists of two separate configurable dividers. The A Divider is a 7-bit divider and can divide by 3 to 129. The B Divider consists of a 9-bit divider followed by a post divider. The 9-bit divider can divide by 12 to 519. The

Contextual Info: DATASHEET ICS674-01 USER CONFIGURABLE DIVIDER Description Features The ICS674-01 consists of two separate configurable dividers. The A Divider is a 7-bit divider and can divide by 3 to 129. The B Divider consists of a 9-bit divider followed by a post divider. The 9-bit divider can divide by 12 to 519. The

674R-01

Abstract: ICS674-01
Contextual Info: DATASHEET ICS674-01 USER CONFIGURABLE DIVIDER Description Features The ICS674-01 consists of two separate configurable dividers. The A Divider is a 7-bit divider and can divide by 3 to 129. The B Divider consists of a 9-bit divider followed by a post divider. The 9-bit divider can divide by 12 to 519. The

Contextual Info: ICS674-01 USER CONFIGURABLE DIVIDER Description Features The ICS674-01 consists of two separate configurable dividers. The A Divider is a 7-bit divider and can divide by 3 to 129. The B Divider consists of a 9-bit divider followed by a post divider. The 9-bit divider can divide

Contextual Info: ICS674-01 USER CONFIGURABLE DIVIDER Description Features The ICS674-01 consists of two separate configurable dividers. The A Divider is a 7-bit divider and can divide by 3 to 129. The B Divider consists of a 9-bit divider followed by a post divider. The 9-bit divider can divide

Contextual Info: ICS674-01 USER CONFIGURABLE DIVIDER Description Features The ICS674-01 consists of two separate configurable dividers. The A Divider is a 7-bit divider and can divide by 3 to 129. The B Divider consists of a 9-bit divider followed by a post divider. The 9-bit divider can divide

Contextual Info: DATASHEET USER CONFIGURABLE DIVIDER I CS6 7 4 -0 1 Description Features The ICS674-01 consists of two separate configurable dividers. The A Divider is a 7-bit divider and can divide by 3 to 129. The B Divider consists of a 9-bit divider followed by a post divider. The 9-bit divider can divide by 12 to 519. The

Contextual Info: ICS674-01 USER CONFIGURABLE DIVIDER Description Features The ICS674-01 consists of two separate configurable dividers. The A Divider is a 7-bit divider and can divide by 3 to 129. The B Divider consists of a 9-bit divider followed by a post divider. The 9-bit divider can divide

ICS674-01

Abstract: ICS673-01 ICS674R-01 ICS674R-01I ICS674R-01IT ICS674R-01T 67401
Contextual Info: ICS674-01 USER CONFIGURABLE DIVIDER Description Features The ICS674-01 consists of two separate configurable dividers. The A Divider is a 7-bit divider and can divide by 3 to 129. The B Divider consists of a 9-bit divider followed by a post divider. The 9-bit divider can divide

Contextual Info: DATASHEET ICS674-01 USER CONFIGURABLE DIVIDER Description Features The ICS674-01 consists of two separate configurable dividers. The A Divider is a 7-bit divider and can divide by 3 to 129. The B Divider consists of a 9-bit divider followed by a post divider. The

Contextual Info: DATA SHEET ICS674-01 ICS674-01 USER CONFIGURABLE DIVIDER USER CONFIGURABLE DIVIDER Description Features The ICS674-01 consists of two separate configurable dividers. The A Divider is a 7-bit divider and can divide by 3 to 129. The B Divider consists of a 9-bit divider

Contextual Info: DATA SHEET ICS558-02 ICS558-02 LVHSTL TO CMOS CLOCK DIVIDER LVHSTL TO CMOS CLOCK DIVIDER Description Features The ICS558-02 accepts a high-speed LVHSTL input and provides four CMOS low skew outputs from a selectable internal divider divide by 3, divide by 4 . The

Contextual Info: ICS558-02 LVHSTL TO CMOS CLOCK DIVIDER Description Features The ICS558-02 accepts a high-speed LVHSTL input and provides four CMOS low skew outputs from a selectable internal divider divide by 3, divide by 4 . The four outputs are split into two banks of two outputs.

"Frequency Divider"

Abstract: Divider modulus SP8789
Contextual Info: SP8789 225MHz Frequency Divider Divided by 20/21 TWO MODULUS DIVIDER Description The SP8789 is a low power programmable ¸20/21 counter.lt divides by 20, when the control input is in the high state and by 21 when in the low state. An internal voltage regulator allows operation from a wide range of supply voltages.

Contextual Info: ICS558-02 INTELTM LVHSTL TO CMOS CLOCK DIVIDER Description Features The ICS558-02 accepts a high speed LVHSTL input and provides four CMOS low skew outputs from a selectable internal divider divide by 3, divide by 4 . The four outputs are split into two banks of two outputs.

DS3738

Abstract: SP8400 SP8401 SP8402 SP8402/KG/MPES
Contextual Info: SP8402 Very Low Phase Noise Divider by 2N DS3738 - 2.1 March 1994 The SP8402 is a very low phase noise divider which divides by powers of two. The S0, S1, S2 data inputs select the division ratio in the range 21 to 28. Special circuits techniques have been

Contextual Info: MITEL SP8402 Very Low Phase Noise Divider by 2N SEMICONDUCTOR DS3738 - 2.1 The SP8402 is a very low phase noise divider which divides by powers of two. The SO, S 1, S2 data inputs select the division ratio in the range 2 1to 28. Special circuits techniques have been

DS3738

Abstract: SP8400 SP8401 SP8402
Contextual Info: SP8402 Very Low Phase Noise Divider by 2N DS3738 The SP8402 is a very low phase noise divider which divides by powers of two. The S0, S1, S2 data inputs select the division ratio in the range 21 to 28. Special circuits techniques have been used to reduce the phase noise

Contextual Info: SP8402 Very Low Phase Noise Divider by 2N DS3738 The SP8402 is a very low phase noise divider which divides by powers of two. The S0, S1, S2 data inputs select the division ratio in the range 21 to 28. Special circuits techniques have been used to reduce the phase noise

SP8402

Abstract: DS3738 SP8400 SP8401
Contextual Info: SP8402 Very Low Phase Noise Divider by 2N DS3738 The SP8402 is a very low phase noise divider which divides by powers of two. The S0, S1, S2 data inputs select the division ratio in the range 21 to 28. Special circuits techniques have been used to reduce the phase noise

DS3738

Abstract: SP8400 SP8401 SP8402
Contextual Info: SP8402 Very Low Phase Noise Divider by 2N DS3738 The SP8402 is a very low phase noise divider which divides by powers of two. The S0, S1, S2 data inputs select the division ratio in the range 21 to 28. Special circuits techniques have been used to reduce the phase noise

Contextual Info: SP8402 Very Low Phase Noise Divider by 2N DS3738 The SP8402 is a very low phase noise divider which divides by powers of two. The S0, S1, S2 data inputs select the division ratio in the range 21 to 28. Special circuits techniques have been used to reduce the phase noise

DS3738

Abstract: SP8400 SP8401 SP8402
Contextual Info: SP8402 Very Low Phase Noise Divider by 2N DS3738 The SP8402 is a very low phase noise divider which divides by powers of two. The S0, S1, S2 data inputs select the division ratio in the range 21 to 28. Special circuits techniques have been used to reduce the phase noise