DOUT14 Search Results

MAX9263

Abstract: MAX9264 prng IEC ACB symbols PJ 62 SPREAD-SPECTRUM SYSTEM
Contextual Info: 19-5644; Rev 1; 3/11 TION KIT EVALUA BLE IL AVA A HDCP Gigabit Multimedia Serial Link Serializer/Deserializer The MAX9263/MAX9264 chipset extends Maxim’s gigabit multimedia serial link GMSL technology to include highbandwidth digital content protection (HDCP) encryption

HSP48901

Abstract: HSP48901JC-30
Contextual Info: HSP48901 Data Sheet July 2004 FN2459.6 3 x 3 Image Filter Features The Intersil HSP48901 is a high speed 9-Tap FIR Filter which utilizes 8-bit wide data and coefficients. It can be configured as a one-dimensional 1-D 9-Tap filter for a variety of signal processing applications, or as a two

Contextual Info: > 4M C C DEVICE SPECIFICATION 33 x 32 1.25 G B IT/S D IFF E R E N T IA L CR O SSPO IN T SW ITCH S2028 GENERAL DESCRIPTION FEATURES 33 x 32 differential crosspoint switch Full broadcast switching capability Differential 10K PECL data path Configurable differential output driver

MIL-A-8625C

Abstract: register file
Contextual Info: DEVICE SPECIFICATION 1 6 x 1 6 1 . 5 G B IT/S D IF F E R E N T IA L C R O SS PO IN T SW ITCH FEATURES • • • • • • • • • S 2016 GENERAL DESCRIPTION 1 6 x 1 6 differential crosspoint switch Full broadcast switching capability DifferentiaMOK PECL data path

GO1555

Abstract: 1kv hd 352M GS1524 GS1560A GS9060 iso 5459 GO1525 w058
Contextual Info: GS1560A/GS1561 HD-LINX II Dual-Rate Deserializer Key Features Description • SMPTE 292M and SMPTE 259M-C compliant descrambling and NRZI → NRZ decoding with bypass • DVB-ASI 8b/10b decoding • auto-configuration for HD-SDI and SD-SDI • serial loop-through cable driver output selectable as

LF3330

Abstract: 200H 201H 202H
Contextual Info: LF3330 LF3330 DEVICES INCORPORATED Vertical Digital Image Filter Vertical Digital Image Filter DEVICES INCORPORATED FEATURES DESCRIPTION ❑ 83 MHz Data Rate ❑ 12-bit Data and Coefficients ❑ On-board Memory for 256 Coefficient Sets ❑ LF InterfaceTM Allows All 256

Contextual Info: The ARM Processor Family This Data Sheet is one of a series describing the ARM Family of products from GEC Plessey Semiconductors. The table below shows the current range of 32-bit RISC M icroprocessors/M icrocontrollers. GPS Name P ackag e Description 32 bit RISC core with 32 bit address range.

Crossbow

Abstract: S 187 S2024B-6 register file DIN31
Contextual Info: DEVICE SPECIFICATION “CROSSBOW” 32 X 32 800 MBIT/S CROSSPOINT SWITCH “CROSSBOW” X 32 800 MBIT/S CROSSPOINT SWITCH BiCMOS PECL 32 CLOCK GENERATOR FEATURES GENERAL DESCRIPTION • Full broadcast switching capability • 32 x 32 crosspoint structure, expandable to 64 x

LF3320

Abstract: LF3320QC12G cf02
Contextual Info: LF3320 LF3320 DEVICES INCORPORATED Horizontal Digital Image Filter Horizontal Digital Image Filter DEVICES INCORPORATED FEATURES DESCRIPTION 83 MHz Data Rate 12-bit Data or Coefficients Expandable to 24-bit 32-Tap FIR Filter, Cascadable for More Filter Taps

LF3320

Abstract: lf3320 r CF1-2
Contextual Info: LF3320 LF3320 DEVICES INCORPORATED Horizontal Digital Image Filter Horizontal Digital Image Filter DEVICES INCORPORATED FEATURES DESCRIPTION 83 MHz Data Rate 12-bit Data or Coefficients Expandable to 24-bit 32-Tap FIR Filter, Cascadable for More Filter Taps

SCSI 100 connector datasheet

Abstract: DIN28 working of 5 pin relay 100 pin scsi 100-pin SCSI female connector n type connector female CB-89200-2 DIN24 relay 5 pin Backup output protect
Contextual Info: DASP-52064 Isolated 32 D/I & 32 D/O Card Features 32 isolated digital inputs for source type 32 interrupt input I/O digital input 32 isolated digital outputs for sink type 2K battery backup RAM for backup nonvolatile data (only for DASP-52064) One programmable timer and interrupt

ADSP-3221

Contextual Info: ANALOG DEVICES High Speed 64-Bit IEEE Floating-Point ALU ADSP-3221 1.1 Scope. This specification covers the detail requirements for a CMOS monolithic 32-bit and 64-bit IEEE Standard 754 format floating-point arithmetic and logic unit ALU . 1.2 Part Number.

Contextual Info: HSP48908/883 33 Two Dimensional Convolver January 1994 Description Features • The Harris HSP48908/883 is a high speed Two Dimensional Convolver which provides a single chip implementation of a video data rate 3 x 3 kernel convolution on two dimensional data. It eliminates the need for external data storage through

Contextual Info: Advance Information S E M I C O N D U C T O R S _ MUAA Routing C o processor RCP Fam ily APPLICATION BENEFITS > > > > > > High performance MAC Address processor for multiport switches and routers (Up to 48 10/100 or 4 Gigabit Ethernet at wire speed)

200H

Abstract: 201H 202H LF3330 VB11
Contextual Info: LF3330 LF3330 DEVICES INCORPORATED Vertical Digital Image Filter Vertical Digital Image Filter DEVICES INCORPORATED FEATURES DESCRIPTION ❑ 83 MHz Data Rate ❑ 12-bit Data and Coefficients ❑ On-board Memory for 256 Coefficient Sets ❑ LF InterfaceTM Allows All 256

AFE8405

Abstract: AFE8405IZDQ CDMA2000-1X
Contextual Info: AFE8405 14-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER www.ti.com SLWS212 – OCTOBER 2008 1 Introduction 1.1 FEATURES • • • • • • • • 14-Bit 85-MSPS High-Performance Single ADC At fin = 140 MHz, SNR ≥ 71 dBFS, SFDR ≥ 79 dBc At fin = 70 MHz, SNR ≥ 73 dBFS,

K3192

Contextual Info: DEVICE SPECIFICATION > FEATURES 4 M C C GENERAL DESCRIPTION 33 x 32 differential crosspoint switch Full broadcast switching capability Differential 10K PECL data path Configurable differential output driver controls Up to 1.25 Gbit/s NRZ data rate TTL configuration controls

SS2024

Abstract: 3111z
Contextual Info: DEVICE SPECIFICATION CROSSBOW” 32 X 32 800 MBIT/S CROSSPOINT SWITCH GENERAL DESCRIPTION FEATURES • Full broadcast switching capability • 32 x 32 crosspoint structure, expandable to 64 x 64 with no external components • ECL 10K data path and TTL I/O for configuration

Contextual Info: LF48908 Two Dimensional Convolver D E V IC E S IN C O R P O R A T E D DESCRIPTION FEATURES . _ _ □ 40 MHz Data and Computation Rate □ Nine Multiplier Array with 8-bit Data and 8-bit Coefficient Inputs □ Separate Cascade Input and Output Ports □ On-board Programmable Row

Contextual Info: 2 HARRIS Ja n u a ry 1991 Features • Single Chip 3x3 Kernel Convolution • Programmable O n-chip Row Buffers • DC to 32 MHz Clock Rate • Cascadable for Larger Kernels and Images • O n-Chip 8-B it ALU • Dual Coefficient Mask Registers, Switchable in a

diode code GW 17

Abstract: AFE8406IZDQ b0107 Video sync splitter vga AFE8406 CDMA2000-1X FIFO181 BGA484
Contextual Info: AFE8406 14-BIT, 85 MSPS DUAL ADC, 8-CHANNEL WIDEBAND RECEIVER www.ti.com SLWS168C – MAY 2005 – REVISED OCTOBER 2008 1 Introduction 1.1 FEATURES • • • • • • • • • 14-Bit 85-MSPS High-Performance Dual ADC Dual ADC Can Be Configured Into Single ADC

LF3320

Abstract: LF3321
Contextual Info: LF3321 Horizontal Digital Image Filter DEVICES INCORPORATED Improved Performance FEATURES Selectable 16-bit Data Output with UserDefined Rounding and Limiting Supports Interleaved Data Streams Supports Decimation up to 16:1 for Increasing Number of Filter Taps

HSP48908

Abstract: HSP48908GC-20 HSP48908GC-32 HSP48908JC-20 HSP48908JC-32 HSP48908VC-20 HSP48908VC-32
Contextual Info: HSP48908 TM Data Sheet May 1999 FN2456.5 Two Dimensional Convolver Features The Intersil HSP48908 is a high speed Two Dimensional Convolver which provides a single chip implementation of a video data rate 3 x 3 kernel convolution on two dimensional data. It eliminates the need for external data storage through

S2002

Abstract: S2004 S2018 S2062 S2064
Contextual Info: DEVICE SPECIFICATION 17 X 17 3.2 GBIT/S DIFFERENTIAL CROSSPOINT SWITCH 17 X 17 3.2 GBIT/S DIFFERENTIAL CROSSPOINT SWITCH • Microwave or fiber-optic data distribution • High-speed automatic test equipment • Datacom or telecom switching FEATURES •