DP840 Search Results

C1995

Abstract: DP8402A DP8402AV DP8403 DP8404 DP8405 V68A SN74ALS632
Contextual Info: August 1989 DP8402A DP8403 DP8404 DP8405 32-Bit Parallel Error Detection and Correction Circuits EDAC’s General Description The DP8402A DP8403 DP8404 and DP8405 devices are 32-bit parallel error detection and correction circuits (EDACs) in 52-pin DP8402A and DP8403 or 48-pin DP8404

C1995

Abstract: DP8408A g2ns ab-9 national
Contextual Info: National Semiconductor Application Brief 9 Tim Garverick Rusty Meier January 1986 If one desires the fastest possible operation of the DP8408A 9A multi-mode dynamic RAM controller driver in accessing DRAMs mode 4 externally controlled access mode should be considered

NS32201

Abstract: cgw RESISTORS op840 hamming encoder IC of XOR GATE tl 2345 ml cgw resistor CIL 108 DP8400-2 DP8400N-2 DP8400V-2
Contextual Info: DP8400-2 National Semiconductor DP8400-2—E2C2 Expandable Error Checker/Corrector General Description memory check bits or DP8400-2S than the single-error cor­ rect configurations. The DP8400-2 has a separate syndrome I/O bus which can be used for error logging or error management. In addition,

D64C

Abstract: DB15C d826 D8-3C DB24-DB31 8535S sot 23 W16 TL 2222 decoder DP8402A DP8403
Contextual Info: PRELIM INARY DP8402A/DP8403/DP8404/DP8405 32-Bit Parallel Error Detection and Correction Circuits EDAC’s General Description The DP8402A, DP8403, DP8404 and DP8405 devices are 32-bit parallel error detection and correction circuits (EDACs) in 52-pin DP8402A and DP8403 or 48-pin DP8404

74F632

Abstract: 74F632QC C1995 DB31 DP8406 DP8406QV V52A F632 Diode cbn 9579
Contextual Info: DP8406 54F 74F632 32-Bit Parallel Error Detection and Correction Circuit General Description The DP8406 device is a 32-bit parallel error detection and correction circuit (EDAC) in a 52-pin or 68-pin package The EDAC uses a modified Hamming code to generate a 7-bit

DP8400N-2

Abstract: DP8400N DP8400 DP8400-2 hamming encoder IC of XOR GATE C1995 74s280 T46D
Contextual Info: DP8400-2 E2C2 Expandable Error Checker Corrector The DP8400-2 Expandable Error Checker and Corrector E2C2 aids system reliability and integrity by detecting errors in memory data and correcting single or double-bit errors The E2C2 data I O port sits across the processormemory data bus as shown and the check bit I O port connects to the memory check bits Error flags are provided

74s409

Abstract: memorias ram SN74S409 DP8409A *LS461 74S40 SM74S409-2 SN74S40
Contextual Info: 256K Dynamic RAM Control le r / Driver SN74S409-2/DP8409A-2 SN74S409/DP8409A F eatu res/ Benefits Ordering Inform ation • All DRAM drive functions on one chip have on-chip hlghcapacitance load drivers specified up to 88 DRAMs • Drives directly all 16K, 64K and 256K DRAMs; capable

NS32201

Abstract: 2d 1002 6 pin dp8409
Contextual Info: DP84412 National SLm Semiconductor DP84412 Dynamic RAM Controller Interface Series Circuit for the Series 32000 CPU Works with all Series 32000 family speed versions up to 10 MHz. Operation of Series 32000 processor at 10 MHz with no WAIT states. Controls DP8409A or DP8419 Mode 5 accesses, hid­

DP8409AN-2

Abstract: DP8409AN DP8409AD-2 dp8409ad DP8409AN2 8409A-2 C1995 D48A DP8409A N48A
Contextual Info: DP8409A Multi-Mode Dynamic RAM Controller Driver General Description Operational Features Dynamic memory system designs which formerly required several support chips to drive the memory array can now be implemented with a single IC the DP8409A MultiMode Dynamic RAM Controller Driver The DP8409A is capable of driving all 16k and 64k Dynamic RAMs DRAMs as

DP8409AN

Abstract: DP8409AD DP8409A D48A N48A V68A interface 64K RAM with 8086 MP dps409
Contextual Info: DP8409A yw\National ÉHASemiconductor DP8409A Multi-Mode Dynamic RAM Controller/Driver General Description Operational Features D ynam ic m em ory system designs, which form erly required several support chips to drive the m em ory array, can now be im plem ented w ith a single 1C . , . the D P8409A M ulti­

Contextual Info: DP8409A 39 National Semiconductor DP8409A Multi-Mode Dynamic RAM Controller/Driver General Description Operational Features Dynamic memory system designs, which formerly required several support chips to drive the memory array, can now be implemented with a single 1C . . . the DP8409A MultiMode Dynamic RAM Controller/Driver. The DP8409A is ca­

DPS-400

Abstract: 68995
Contextual Info: DP8400-2 National Semiconductor DP8400-2—E2C2 Expandable Error Checker/Corrector General Description memory check bits or DP8400-2S than the single-error cor­ rect configurations. The DP8400-2 Expandable Error Checker and Corrector E2C2 aids system reliability and integrity by detecting er­

C1995

Abstract: DP8402A DP8402AV DP8403 DP8404 DP8405 V68A
Contextual Info: August 1989 DP8402A DP8403 DP8404 DP8405 32-Bit Parallel Error Detection and Correction Circuits EDAC’s General Description Features Y Y Y Y Y ol Y Detects and corrects single-bit errors Detects and flags double-bit errors Built-in diagnostic capability

74s409

Contextual Info: 256K D y n a m ic R A M SN74S409-2/DP8409A-2 s n 74S409/ d p 8409 a C o n t r o lle r / D r iv e r O rdering Inform ation F e a tu re s / B enefits • All DRAM drive functions on one chip have on-chip highcapacitance load drivers specified up to 88 DRAMs

ic 74xx

Abstract: 74AS04 DP8409 74XX C1995 DP8408A DP8409A DP8417 Dynamic Memory Refresh Controller hidden refresh
Contextual Info: The DP8408A DP8409A dynamic RAM controllers have been well received by dynamic memory users because they perform functions formerly requiring multiple integrated circuit chips These controllers are designed to be suitable for a variety of DRAM control methods As a result of the many

DP8408AD

Contextual Info: DP8408A EH National Semiconductor DP8408A Dynamic RAM Controller/Driver General Description Operational Features Dynamic memory system designs, which formerly required several support chips to drive the memory array, can now be implemented with a single 1C , . . the DP8408A Dynamic

Contextual Info: DP8400-2 5 National Semiconductor DP8400-2—E2C2 Expandable Error Checker/Corrector General Description The DP8400-2 Expandable Error Checker and Corrector E2C2 aids system reliability and integrity by detecting er­ rors in memory data and correcting single or double-bit er­

NS32016

Abstract: NS32201 74LS244 uses and functions 74ls164 DP8400 74LS374 DATASHEET ic 74ls164 AND SPECIFICATIONS ic 8400 CPU IC 74ls244 latch datasheet IC 74LS374 using in led interfacing
Contextual Info: National Semiconductor Application Note 387 Webster Rusty Meier December 1985 INTRODUCTION Three PAL’s (Programmable Array Logic devices) were used in this application in order to interface between the NS32016 DP8419 and the DP8400 to produce an error correcting memory system for the Series 32000 microprocessor family The PAL Interface Controller (hereafter referred

74ALS533

Abstract: dp8400 AN-308 74S30 C1995
Contextual Info: National Semiconductor Application Note 308 Chuck Pham October 1984 The purpose of this Application Note is to provide memory designers with detailed information on the DP8400 parallel expansion method This method allows fast check bit generation error detection and error correction A thorough understanding of the 16-bit implementation is a prerequisite

D52A

Contextual Info: DP8402A,DP8403,DP8404,DP8405 DP8402A/DP8403/DP8404/DP8405 32-Bit Parallel Error Detection and Correction Circuits EDAC's Literature Number: SNOSBX3A August 1989 DP8402A DP8403 DP8404 DP8405 32-Bit Parallel Error Detection and Correction Circuits (EDAC’s)

DMPAL16R4

Abstract: dp84300 68000 memory DP8409A DP8408
Contextual Info: DP84322 £ 2 National Semiconductor DP84322 Dynamic RAM Controller Interface Circuit for the 68000 CPU General Description Features The DP84322 dynamic RAM controller interface is a Pro­ grammable Array Logic PAL device which allows for easy interface between the DP8409A, 17 ,18,19, 28, 29 dynamic

dp8409

Abstract: 74S409 SN74S409-2/DP8409A-2
Contextual Info: a SN74S409-2/DP8409A-2 SN74S409/DP8409A Advanced Micro Devices 256K Dynamic RAM Controller/Driver PIN CONFIGURATION DISTINCTIVE CHARACTERISTICS • ■ All DRAM drive functions on one chip have on-chlp hlgh-capacltance load drivers specified up to 88 DRAMs

S40S

Abstract: AN-305 DP8408A DP8408AD DP8408AN DP8408AN-3 rasistor 8408a
Contextual Info: DP8408A CT1 National Jit Semiconductor DP8408A Dynamic RAM Controller/Driver General Description Operational Features D ynam ic m em ory system designs, w hich form erly required several support chips to drive the m em ory array, can now be im plem ented w ith a single 1C . . . the DP8408A Dynamic

68000 memory

Abstract: dynamic ram controller DP84300 DP84322N DMPAL16R4 C1995 DP8409A DP84322 DP84322J J20A
Contextual Info: DP84322 Dynamic RAM Controller Interface Circuit for the 68000 CPU General Description Features The DP84322 dynamic RAM controller interface is a Programmable Array Logic PAL device which allows for easy interface between the DP8409A 17 18 19 28 29 dynamic