DQB 213 Search Results

Contextual Info: CY7C4122KV13/CY7C4142KV13 144-Mbit QDR -IV XP SRAM 144-Mbit QDR™-IV GT SRAM Features • Configurations CY7C4122KV13 – 8 M x 18 144-Mbit density 8 M × 18, 4 M × 36 [1] ■ Total Random Transaction Rate of 2132 MT/s ■ Maximum operating frequency of 1066 MHz

Contextual Info: CY7C4122KV13/CY7C4142KV13 144-Mbit QDR -IV XP SRAM 144-Mbit QDR™-IV GT SRAM Features • Configurations CY7C4122KV13 – 8 M x 18 144-Mbit density 8 M × 18, 4 M × 36 [1] ■ Total Random Transaction Rate of 2132 MT/s ■ Maximum operating frequency of 1066 MHz

Contextual Info: CY7C4122KV13/CY7C4142KV13 144-Mbit QDR -IV XP SRAM 144-Mbit QDR™-IV XP SRAM Features • Configurations CY7C4122KV13 – 8 M x 18 144-Mbit density 8 M × 18, 4 M × 36 [1] ■ Total Random Transaction Rate of 2132 MT/s ■ Maximum operating frequency of 1066 MHz

Contextual Info: CY7C4022KV13/CY7C4042KV13 72-Mbit QDR -IV XP SRAM 72-Mbit QDR™-IV XP SRAM Features • Configurations 72-Mbit density 4 M x 18, 2 M × 36 [1] CY7C4022KV13 – 4 M × 18 ■ Total Random Transaction Rate of 2132 MT/s ■ Maximum operating frequency of 1066 MHz

74AS871

Contextual Info: TEXAS INSTR LOGIC NOTICE SEE ORDER OF DATA FOR ERRATA ESE D • fiU17S3 QOflBTEE 1 ■ T-Vg-0?-0? S N 5 4 A LS 8 70 , SN 5 4AS 8 70 , S N 5 4 A LS 8 71, SN 5 4 A S 8 71 S N 74 A LS 8 70 , S N 74 A S 8 70 , S N 7 4 A L S 8 7 1 , S N 74 A S 8 71 INFORMATION

CY7C1347F

Abstract: CY7C1347F-200AC CY7C1347F-225AC CY7C1347F-225BGC CY7C1347F-250AC CY7C1347F-250BGC
Contextual Info: CY7C1347F 4-Mbit 128K x 36 Pipelined Sync SRAM Functional Description[1] Features • Fully registered inputs and outputs for pipelined operation • 128K by 36 common I/O architecture The CY7C1347F is a 3.3V, 128K by 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache

CY7C1347F

Abstract: CY7C1347F-200AC CY7C1347F-225AC CY7C1347F-225BGC CY7C1347F-250AC CY7C1347F-250BGC
Contextual Info: CY7C1347F 4-Mbit 128K x 36 Pipelined Sync SRAM Functional Description[1] Features • Fully registered inputs and outputs for pipelined operation • 128K by 36 common I/O architecture The CY7C1347F is a 3.3V, 128K by 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache

Contextual Info: 64K X 18, 32K x 32/36 3.3V I/O, F L O W -T H R O U G H S Y N C B U R S T SRAM I^ IIC R D N MT58LC64K18B3, MT58LC32K32B3, MT58LC32K36B3 SYNCBURST SRAM 3.3V Supply, Flow-Through and Burst Counter SYNCBURST SRAM FEATURES • • • • • • • • • •

Contextual Info: ADVANCE M I^ P n M 8 I 8Mb: 512K x 18, 256K x 32/36 PIPELINED ZBT SRAM MT55L512L18P, MT55L256L32P, MT55L256L36P; MT55L512V18P, MT55L256V32P, MT55L256V36P 8Mb ZBT SRAM 3.3V V dd, 3.3V or 2.5V I/O, Selectable Burst Mode FEATURES H ig h frequency an d 100 p ercen t bu s utilization

Contextual Info: ADVANCE 128K x 18, 64 K x 32/36 3.3V I/O, PIPELINED. SCD S Y N C B U R S T SR AM I^ IC R D N MT58LC128K18D9, MT58LC64K32D9, MT58LC64K36D9 SYNCBURST SRAM 3.3V Supply, Pipelined, Burst Counter and Single-Cycle Deselect SYNCBURST SRAM FEATURES • Fast access times: 3.5ns, 3.8ns, 4.2ns, 4.5ns and 6ns

CY7C1339F

Abstract: CY7C1339F-225AC CY7C1339F-225BGC CY7C1339F-250AC CY7C1339F-250AI CY7C1339F-250BGC CY7C1339F-250BGI
Contextual Info: CY7C1339F 4-Mbit 128K x 32 Pipelined Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • 128K x 32 common I/O architecture • 3.3V core power supply • 2.5V / 3.3V I/O operation • Fast clock-to-output times

three input OR gate

Abstract: A101 CY7C1214F CY7C1214F-100AC
Contextual Info: CY7C1214F 1-Mb 32K x 32 Flow-Through Sync SRAM Features • 32K X 32 common I/O • 3.3V –5% and +10% core power supply (VDD) • 3.3V I/O supply (VDDQ) • Fast clock-to-output times — 7.5 ns (117-MHz version) — 8.5 ns (100-MHz version) • Provide high-performance 2-1-1-1 access rate

CY7C1339F

Abstract: CY7C1339F-225AC CY7C1339F-225BGC CY7C1339F-250AC CY7C1339F-250AI CY7C1339F-250BGC CY7C1339F-250BGI 119284
Contextual Info: CY7C1339F 4-Mbit 128K x 32 Pipelined Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • 128K x 32 common I/O architecture • 3.3V core power supply • 2.5V / 3.3V I/O operation • Fast clock-to-output times

A101

Abstract: CY7C1214F CY7C1214F-100AC
Contextual Info: CY7C1214F 1-Mb 32K x 32 Flow-Through Sync SRAM Features • 32K X 32 common I/O • 3.3V –5% and +10% core power supply (VDD) • 3.3V I/O supply (VDDQ) • Fast clock-to-output times — 7.5 ns (117-MHz version) — 8.5 ns (100-MHz version) • Provide high-performance 2-1-1-1 access rate

A101

Abstract: CY7C1297F CY7C1297F-117AC
Contextual Info: CY7C1297F 1-Mbit 64K x 18 Flow-Through Sync SRAM Features • 64K x 18 common I/O • 3.3V –5% and +10% core power supply (VDD) • 3.3V I/O supply (VDDQ) • Fast clock-to-output times — 6.5 ns (133-MHz version) — 7.5 ns (117-MHz version) • Provide high-performance 2-1-1-1 access rate

A101

Abstract: CY7C1336F CY7C1336F-117AC
Contextual Info: CY7C1336F 2-Mbit 64K x 32 Flow-Through Sync SRAM Functional Description[1] Features • 64K x 32 common I/O • 3.3V –5% and +10% core power supply (VDD) • 3.3V I/O supply (VDDQ) • Fast clock-to-output times — 6.5 ns (133-MHz version) — 7.5 ns (117-MHz version)

A101

Abstract: CY7C1329G CY7C1329G-133AC CY7C1329G-166AC
Contextual Info: CY7C1329G 2-Mb 64K x 32 Pipelined Sync SRAM Features • Registered inputs and outputs for pipelined operation • 64K x 32 common I/O architecture • 3.3V core power supply • 2.5V I/O operation • Fast clock-to-output times counter for internal burst operation. All synchronous inputs are

A101

Abstract: CY7C1217F CY7C1217F-100AC
Contextual Info: CY7C1217F 1-Mbit 32K x 36 Flow-Through Sync SRAM Features • 32K x 36 common I/O • 3.3V –5% and +10% core power supply (VDD) • 3.3V I/O supply (VDDQ) • Fast clock-to-output times — 7.5 ns (117-MHz version) — 8.0 ns (100-MHz version) • Provide high-performance 2-1-1-1 access rate

A101

Abstract: CY7C1344F CY7C1344F-100AC
Contextual Info: CY7C1344F 2-Mbit 64K x 36 Flow-Through Sync SRAM Functional Description[1] Features • 64K x 36 common I/O • 3.3V –5% and +10% core power supply (VDD) • 3.3V I/O supply (VDDQ) • Fast clock-to-output times — 7.5 ns (117-MHz version) — 8.0 ns (100-MHz version)

A101

Abstract: CY7C1336F CY7C1336F-117AC
Contextual Info: CY7C1336F 2-Mbit 64K x 32 Flow-Through Sync SRAM Functional Description[1] Features • 64K x 32 common I/O • 3.3V –5% and +10% core power supply (VDD) • 3.3V I/O supply (VDDQ) • Fast clock-to-output times — 6.5 ns (133-MHz version) — 7.5 ns (117-MHz version)

A101

Abstract: CY7C1329G CY7C1329G-133AC CY7C1329G-166AC
Contextual Info: CY7C1329G 2-Mb 64K x 32 Pipelined Sync SRAM Features • Registered inputs and outputs for pipelined operation • 64K x 32 common I/O architecture • 3.3V core power supply • 2.5V I/O operation • Fast clock-to-output times counter for internal burst operation. All synchronous inputs are

A101

Abstract: CY7C1297F CY7C1297F-117AC
Contextual Info: CY7C1297F 1-Mbit 64K x 18 Flow-Through Sync SRAM Features • 64K x 18 common I/O • 3.3V –5% and +10% core power supply (VDD) • 3.3V I/O supply (VDDQ) • Fast clock-to-output times — 6.5 ns (133-MHz version) — 7.5 ns (117-MHz version) • Provide high-performance 2-1-1-1 access rate

A101

Abstract: CY7C1217F CY7C1217F-100AC
Contextual Info: CY7C1217F 1-Mbit 32K x 36 Flow-Through Sync SRAM Features • 32K x 36 common I/O • 3.3V –5% and +10% core power supply (VDD) • 3.3V I/O supply (VDDQ) • Fast clock-to-output times — 7.5 ns (117-MHz version) — 8.0 ns (100-MHz version) • Provide high-performance 2-1-1-1 access rate

A101

Abstract: CY7C1346F CY7C1346F-100AC CY7C1346F-133AC CY7C1346F-166AC
Contextual Info: CY7C1346F 2-Mbit 64K x 36 Pipelined Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • 64K x 36 common I/O architecture • 3.3V core power supply • 3.3V I/O operation • Fast clock-to-output times