DRR1 Search Results

Contextual Info: Thai H E W L E T T WLHMPA C K A R D D igital Radio Receiver Down Converter M odules for 21.2 to 23.6 GHz Technical Data DRR1-23XX Features Description • Low N oise PHEMT MMIC Front End Amplifier This digital radio receiver module provides the RF receive and down

DRR1-38XX

Abstract: receiver 20 GHz block Diagram
Contextual Info: Digital Radio Receiver Down Converter Modules for 37 to 40␣ GHz Technical Data DRR1-38XX Features Description • Low Noise PHEMT MMIC Front End Amplifier This digital radio receiver module provides the RF receive and down conversion function for 38 GHz

Contextual Info: What H EW LETT* mLlíM P A C K A R D Digital Radio Receiver Down Converter Modules for 37 to 40 GHz Technical Data DRR1-38XX Features • Low Noise PHEMTMMIC Front End Amplifier • Image Reject Mixer • Integrated Silicon Bipolar VCO Local Oscillator • Low Phase Noise

Contextual Info: VZ3I H E W L E T T KfSI PACKARD Digital Radio Receiver Down Converter Modules for 37 to 40 GHz Technical Data DRR1-38XX Features Description • Low N oise PHEMT MMIC F ron t End A m plifier This digital radio receiver module provides the RF receive and down

DRR1-23XX

Abstract: MSA-1100 hp mmic Image Reject Mixer
Contextual Info: Digital Radio Receiver Down Converter Modules for 21.2 to 23.6 GHz Technical Data DRR1-23XX Features Description • Low Noise PHEMT MMIC Front End Amplifier This digital radio receiver module provides the RF receive and down conversion function for 23 GHz

Contextual Info: That HEW LETT WHkM PA CK A R D Digital Radio Receiver Down Converter Modules for 37 to 40 GHz Technical Data DRR1-38XX Features Description • Low Noise PHEMT MMIC Front End Amplifier • Image Reject Mixer • Integrated Silicon Bipolar VCO Local Oscillator

DRR1-23XX

Abstract: DRR1-38XX
Contextual Info: Receiver Down Converter Modules Part Number DRR1-23XX DRR1-38XX RF Tuning Range GHz IF Frequency (MHz) Min. Gain (dB) Gain Flatness (dB) Noise Figure (dB) Power Input at P1dB (dBm) Page No. 21.2 to 23.6 37 to 40 630 or 1260 630 or 1260 18 18 ±1 ±1 4.5

DRR1-23XX

Abstract: MSA-1100 receiver 20 GHz block Diagram
Contextual Info: Digital Radio Receiver Down Converter Modules for 21.2 to 23.6 GHz Technical Data DRR1-23XX Features Description • Low Noise PHEMT MMIC Front End Amplifier This digital radio receiver module provides the RF receive and down conversion function for 23 GHz

Contextual Info: VZ3I HEW LETT m íflM PACKARD Digital Radio Receiver Down Converter Modules for 21.2 to 23.6 GHz Technical Data DRR1-23XX Features • Low N oise PHEMT MMIC Front End Am plifier • Image Reject M ixer • Integrated Silicon Bipolar VCO Local O scillator • Low Phase Noise

Contextual Info: WtittI H EW L E T T WÜKM PA CK A R D Digital Radio Receiver Down Converter Modules for 21.2 to 23.6 GHz Technical Data DRR1-23XX Features Description • Low Noise PHEMT MMIC Front End Amplifier • Image Reject Mixer This digital radio receiver module provides the RF receive and down

DRR1-38XX

Contextual Info: Digital Radio Receiver Down Converter Modules for 37 to 40 GHz Technical Data DRR1-38XX Features Description • Low Noise PHEMT MMIC Front End Amplifier This digital radio receiver module provides the RF receive and down conversion function for 38 GHz digital radios.

Contextual Info: ¥tio% HEW LETT* mitíM P A C K A R D Digital Radio R eceiver Down Converter M odules for 37 to 40 GHz Technical Data DRR1-38XX F ea tu res D escrip tion • Low Noise PHEMT MMIC Front End Amplifier • Image Reject Mixer • Integrated Silicon Bipolar VCO Local Oscillator

VTO-8060

Abstract: VTO-8080
Contextual Info: Wireless Infrastructure Products Selection Guide Digital Radio Modules Receiver Down Converter Modules Part Number RF Tuning Range GHz IF Frequency (MHz) Min. Gain (dB) Gain Flatness Noise Figure (dB) Power Input at P1 dB (dBm) DRR1-23XX 21.2 to 23.6 630 or 1260

multibus ARCHITECTURE

Abstract: mcbsp tms 6000
Contextual Info: TMS320VC5416 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS095B – MARCH 1999 – REVISED OCTOBER 1999 D D D D D D D D D D D D D Advanced Multibus Architecture With Three Separate 16-Bit Data Memory Buses and One Program Memory Bus 40-Bit Arithmetic Logic Unit ALU

Contextual Info: TMS320VC5416 FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR SPRS095E – MARCH 1999 – REVISED MAY 2000 D D D D D D D D D D D D D Separate 16-Bit Data Memory Buses and One Program Memory Bus 40-Bit Arithmetic Logic Unit ALU Including a 40-Bit Barrel Shifter and Two

ifr 422 H7

Abstract: ifr 422 h6 49 4h10 remote TMS320C54xTM
Contextual Info: TMS320VC5441 Fixed-Point Digital Signal Processor Data Manual Literature Number: SPRS122A December 1999 – Revised November 2000 PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to

TMS320LC546A

Contextual Info: HEADER LINE 1 FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS039C – FEBRUARY 1996 – REVISED DECEMBER 1999 D Advanced Multibus Architecture With Three D D D D D D D D D D D D D D D D D D Separate 16-Bit Data Memory Buses and One Program Memory Bus 40-Bit Arithmetic Logic Unit ALU

Contextual Info: TMS320F2810, TMS320F2811, TMS320F2812 TMS320C2810, TMS320C2811, TMS320C2812 Digital Signal Processors Data Manual Literature Number: SPRS174N April 2001 − Revised May 2006 PRODUCTION DATA information is current as of publication date. Products conform to

Contextual Info: www.ti.com TMS320DM642 Video/Imaging Fixed-Point Digital Signal Processor SPRS200J – JULY 2002 – REVISED AUGUST 2005 1 TMS320DM642 Video/Imaging Fixed-Point Digital Signal Processor 1.1 • • • • • • Features High-Performance Digital Media Processor

TMS320VC541

Contextual Info: SM320VC5416-EP Fixed-Point Digital Signal Processor Data Manual Literature Number: SGUS048 July 2003 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include

tms320vC5402 starter kit

Abstract: BDX 34 TMS320VC5402
Contextual Info: TMS320VC5402 FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 D Advanced Multibus Architecture With Three D D D D D D D D D D D D D Separate 16-Bit Data Memory Buses and One Program Memory Bus 40-Bit Arithmetic Logic Unit ALU ,

TEXAS INSTRUMENTS, Mold Compound, CSP

Contextual Info: SM320C6202ĆEP FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR SGUS044–JULY 2003 D Controlled Baseline D D D D D D D D D D 3M-Bit On-Chip SRAM – One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of –40°C to 105°C Enhanced Diminishing Manufacturing

Contextual Info: SMJ320C6203 FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR SGUS033 – FEBRUARY 2002 D High-Performance Fixed-Point Digital D D D D D Signal Processor DSP – SMJ320C62x – 5-ns Instruction Cycle Time – 200-MHz Clock Rate – Eight 32-Bit Instructions/Cycle

Contextual Info: TMS320VC5502 Fixed-Point Digital Signal Processor Data Manual Literature Number: SPRS166I April 2001 – Revised January 2006 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not