DS058 Search Results

XC9536XL

Abstract: XAPP114 XAPP427 XC9500XL XC9536 Pb-Free Marking Codes XC9536XL VQFP XC9536XL-10VQ64C VQG44 XC9536XL-10VQ44
Contextual Info: XC9536XL High Performance CPLD R DS058 v1.7 July 15, 2005 5 Product Specification Features Power Estimation • • • • Power dissipation in CPLDs can vary substantially depending on the system frequency, design application and output loading. To help reduce power dissipation, each macrocell

XC9536XL

Abstract: XC9536 PC44 VQ44 XC9500XL
Contextual Info: XC9536XL High Performance CPLD DS058 v1.2 June 25, 2001 5 Features • • • • • • • • • • • 5 ns pin-to-pin logic delays System frequency up to 178 MHz 36 macrocells with 800 usable gates Available in small footprint packages - 44-pin PLCC (34 user I/O pins)

54V18

Contextual Info: XC9536XL High Performance CPLD R DS058 v1.3 October 21, 2002 5 Product Specification Features Power Estimation • • • • Power dissipation in CPLDs can vary substantially depending on the system frequency, design application and output loading. To help reduce power dissipation, each macrocell

PC44

Abstract: XAPP114 XC9500XL XC9536 XC9536XL XC9536XL-7CS48I XC9536XL-10CS48C
Contextual Info: XC9536XL High Performance CPLD R DS058 v1.4 August 21, 2003 5 Preliminary Product Specification Features Power Estimation • • • • Power dissipation in CPLDs can vary substantially depending on the system frequency, design application and output loading. To help reduce power dissipation, each macrocell

XC9536XL

Abstract: 95xxxXL XC9536XL VQFP xc9536xl-5 XC9536XL-10VQ44 XAPP427 VQG44 XC9536XL-5PCG44C XC9500XL XC9536XL-7PC44C
Contextual Info: XC9536XL High Performance CPLD R DS058 v1.9 April 3, 2007 Features • • • • • • • • • • • 5 ns pin-to-pin logic delays System frequency up to 178 MHz 36 macrocells with 800 usable gates Available in small footprint packages - 44-pin PLCC (34 user I/O pins)

XC9536XL

Abstract: PC44 XC9500XL XC9536 VQ64
Contextual Info: XC9536XL High Performance CPLD DS058 v1.1 August 28, 2000 5 Features • • • • • • • • • • • 4 ns pin-to-pin logic delays System frequency up to 200 MHz 36 macrocells with 800 usable gates Available in small footprint packages - 44-pin PLCC (34 user I/O pins)

VQG44

Abstract: XC9536XL-10VQ44I XC9536XL 84 PLCC pin configuration XAPP114 XAPP427 XC9500XL XC9536 xc9536 44 pin vqfp
Contextual Info: XC9536XL High Performance CPLD R DS058 v1.6 September 15, 2004 5 Preliminary Product Specification Features Power Estimation • • • • Power dissipation in CPLDs can vary substantially depending on the system frequency, design application and output

Contextual Info: XC9536XL High Performance CPLD DS058 v1.1 August 28, 2000 5 Features • • • • • • • • • • • 4 ns pin-to-pin logic delays System frequency up to 200 MHz 36 macrocells with 800 usable gates Available in small footprint packages - 44-pin PLCC (34 user I/O pins)

V18 marking

Abstract: XC9536XL-5VQ44C VQG44
Contextual Info: XC9536XL High Performance CPLD R DS058 v1.8 March 22, 2006 Product Specification Features Power Estimation • • • • Power dissipation in CPLDs can vary substantially depending on the system frequency, design application and output loading. To help reduce power dissipation, each macrocell

Contextual Info: XC9536XL High Performance CPLD R DS058 v1.5 July 15, 2004 5 Preliminary Product Specification Features Power Estimation • • • • Power dissipation in CPLDs can vary substantially depending on the system frequency, design application and output loading. To help reduce power dissipation, each macrocell

XC9536XL5CS48C

Contextual Info: XC9536XL High Performance CPLD R DS058 v1.3 June 18, 2003 5 Preliminary Product Specification Features Power Estimation • • • • Power dissipation in CPLDs can vary substantially depending on the system frequency, design application and output loading. To help reduce power dissipation, each macrocell

XC9536XL VQFP pinout

Abstract: XC9536XL pinout PC44 VQ44 XC9500XL XC9536 XC9536XL
Contextual Info: XC9536XL High Performance CPLD R DS058 v1.2 June 25, 2001 Preliminary Product Specification Features cations and computing systems. It is comprised of two 54V18 Function Blocks, providing 800 usable gates with propagation delays of 5 ns. See Figure 2 for architecture

54V18

Contextual Info: XC9536XL High Performance CPLD R DS058 v1.2 June 20, 2002 5 Preliminary Product Specification Features Power Estimation • • • • Power dissipation in CPLDs can vary substantially depending on the system frequency, design application and output loading. To help reduce power dissipation, each macrocell

XC95144XL-10TQ144I

Abstract: XC95144XL-10TQG100C XAPP114 XAPP427 XC9500XL XC95144 XC95144XL XC95144XL-5-CS144 XC95144XL-5TQ100 xc95144xl tq144
Contextual Info: XC95144XL High Performance CPLD R DS056 v1.8 July 15, 2005 5 Product Specification Features Power Estimation • • • • Power dissipation in CPLDs can vary substantially depending on the system frequency, design application and output loading. To help reduce power dissipation, each macrocell

national timer switch tb 179

Abstract: national timer tb 179 LMX5251 dmc 20 deutsch dmc 22 deutsch ds071 DS101 fm transistor radio mini project CP3BT10 CP3BT10G38
Contextual Info: CP3BT10 Reprogrammable Connectivity Processor with Bluetooth and USB Interfaces 1.0 General Description The CP3BT10 connectivity processor combines high performance with the massive integration needed for embedded Bluetooth applications. A powerful RISC core with on-chip

XC95288XL10TQG144I pinout

Abstract: XC95288XL PQG208 XC95288XL pinout XC95288XL-10TQG144C fgg256 XC95288XL XC95288XL-7CS280C XC95288XL-10FGG256I XC95288XL-7TQ144I pqg208
Contextual Info: XC95288XL High Performance CPLD R DS055 v2.1 April 3, 2007 5 Features • • • • • • • • • • • 6 ns pin-to-pin logic delays System frequency up to 208 MHz 288 macrocells with 6,400 usable gates Available in small footprint packages - 144-pin TQFP (117 user I/O pins

DS058

Contextual Info: e T & D TECHNOLOGI ES SSE D • llflSOÖ3 00 ]032fl 521 ■ BTDT T-m-n PRELIMINARY T E C H N O L O G I E S RCV1201-1.2 FIBER OPTIC "LIGHT TO LOGIC " RECEIVER Features: Applications: ■ "Light to Logic "™ 28-pin DIP receiver offers ECL compatibility.

DS600

Abstract: XA95144XL AEC-Q100 XA9500XL XAPP114 XAPP427 XC9500XL Xa9500 2N6210
Contextual Info: XA95144XL Automotive CPLD DS600 v1.1 April 3, 2007 Features • • • • • • • • • • • • AEC-Q100 device qualification and full PPAP support available in I-grade. Guaranteed to meet full electrical specifications over TA = -40° C to +85° C (I-grade)

Contextual Info: CP3CN17 CP3CN17 Reprogrammable Connectivity Processor with CAN Interface Literature Number: SNOSA98B CP3CN17 Reprogrammable Connectivity Processor with CAN Interface 1.0 General Description The CP3CN17 connectivity processor combines a powerful RISC core with on-chip SRAM and Flash memory for high

F300H

Abstract: FC44H BIT137
Contextual Info: CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces 1.0 General Description The CP3BT23 connectivity processor combines high performance with the massive integration needed for embedded Bluetooth applications. A powerful RISC core with on-chip

USB cable AWM 2725 rx tx pinout

Contextual Info: CP3BT26 CP3BT26 Reprogrammable Connectivity Processor with Bluetooth, USB, and CAN Interfaces Literature Number: SNOSAE5C CP3BT26 Reprogrammable Connectivity Processor with Bluetooth , USB, and CAN Interfaces 1.0 General Description The CP3BT26 connectivity processor combines high performance with the massive integration needed for embedded

F1A4

Abstract: TR-28 national timer switch tb 208
Contextual Info: CP3BT26 Reprogrammable Connectivity Processor with Bluetooth , USB, and CAN Interfaces 1.0 General Description The CP3BT26 connectivity processor combines high performance with the massive integration needed for embedded Bluetooth applications. A powerful RISC core with on-chip

Contextual Info: CP3UB17 CP3UB17 Reprogrammable Connectivity Processor with USB Interface Literature Number: SNOSA99C CP3UB17 Reprogrammable Connectivity Processor with USB Interface 1.0 General Description The CP3UB17 connectivity processor combines a powerful RISC core with on-chip SRAM and Flash memory for high

XC95144XL-10TQG100C

Abstract: XC95144XL-10TQ100I XC95144XL-10CSG144C XC95144XL-10TQ144I XC95144XL-5-TQ100 XC95144XL-10TQG144C xc95144xl XC95144XL-10TQG100I XC95144XL-7TQ100C TQFP 100 PACKAGE footprint
Contextual Info: XC95144XL High Performance CPLD R DS056 v2.0 April 3, 2007 Features • • • • • • • • • • • 5 ns pin-to-pin logic delays System frequency up to 178 MHz 144 macrocells with 3,200 usable gates Available in small footprint packages - 100-pin TQFP (81 user I/O pins)