DS261 Search Results

Contextual Info: DS26101 8-Port Transmission Convergence Device www.maxim-ic.com GENERAL DESCRIPTION FEATURES On the transmit side, the DS26101 receives ATM cells from an ATM device through a UTOPIA II interface, provides cell buffering up to 4 cells , HEC generation and insertion, cell scrambling, and converts the data

motorola bts maintenance

Abstract: g6017
Contextual Info: DS26101 8-Port Transmission Convergence Device www.maxim-ic.com GENERAL DESCRIPTION FEATURES On the transmit side, the DS26101 receives ATM cells from an ATM device through a UTOPIA II interface, provides cell buffering up to 4 cells , HEC generation and insertion, cell scrambling, and converts the data

SAD 512

Abstract: CS61584A SAD assembly cirrus Logic Marking Code
Contextual Info: 11/16/00 Errata: CS61584A Revision E Reference CS61584A Data Sheet revision DS261PP4 dated JAN ‘99 This document lists the errata for Revision E of the CS61584A device, and describes the differences between Revision E and the referenced Data Sheet. 1. Quartz Crystal Loading Issue

11-B

Abstract: 11-D DS26101
Contextual Info: DS26101 8-Port Transmission Convergence Device www.maxim-ic.com GENERAL DESCRIPTION FEATURES On the transmit side, the DS26101 receives ATM cells from an ATM device through a UTOPIA II interface, provides cell buffering up to 4 cells , HEC generation and insertion, cell scrambling, and converts the data

RLCD14

Abstract: RLCD10
Contextual Info: DS26102 16-Port Transmission Convergence Device www.maxim-ic.com GENERAL DESCRIPTION FEATURES On the transmit side, the DS26102 receives ATM cells from an ATM device through a UTOPIA II interface, provides cell buffering up to 4 cells , HEC generation and insertion, cell scrambling, and converts the data

crystal oscillator marking

Abstract: CS61584A
Contextual Info: 02/10/99 Errata: CS61584A Revision D Reference CS61584A Data Sheet revision DS261PP4 dated JAN ‘99 This document is an errata for Revision D of the CS61584A device, and describes the differences between Revision D and the referenced data sheet. Revision E is expected to

11-B

Abstract: 11-D DS26101 bts 122 E1 frame
Contextual Info: DS26101 8-Port TDM-to-ATM PHY www.maxim-ic.com GENERAL DESCRIPTION FEATURES On the transmit side, the DS26101 receives ATM cells from an ATM device through a UTOPIA II interface, provides cell buffering up to 4 cells , HEC generation and insertion, cell scrambling, and converts the data

11-D

Abstract: DS26102 11-B RLCD10 E1 frame
Contextual Info: DS26102 16-Port Transmission Convergence Device www.maxim-ic.com GENERAL DESCRIPTION FEATURES On the transmit side, the DS26102 receives ATM cells from an ATM device through a UTOPIA II interface, provides cell buffering up to 4 cells , HEC generation and insertion, cell scrambling, and converts the data

DS21352

Abstract: DS21354 DS21455 DS21458 DS2155 DS21552 DS21554 DS2156 DS26101 DS26102
Contextual Info: Maxim/Dallas > App Notes > TELECOM Keywords: Loopback, loopback operation, DS2156, DS26101, DS26102, Utopia, LLB, RLB, FLB, PLB, DLB, local loopback, remote loopback, framer loopback, payload loopback, diagnostic loopback, per-channel loopback Sep 10, 2004

DS-261

Abstract: dma controller VERILOG DS261 PCI-X verilog code for pci halfbridge design 4 channels design of dma controller using verilog
Contextual Info: DS261 v1.0 June 23, 2003 PCI-X/PCI HalfBridge Reference Design for Virtex-II Pro, Virtex-II, and Virtex-E FPGAs Product Overview Features • Asynchronous clocks for PCI-X and FPGA operation • • Up to eight DMA Controller(s) Free with purchase of Xilinx PCI-X 64/66 Core

Contextual Info: DS26102 16-Port Transmission Convergence Device www.maxim-ic.com GENERAL DESCRIPTION FEATURES On the transmit side, the DS26102 receives ATM cells from an ATM device through a UTOPIA II interface, provides cell buffering up to 4 cells , HEC generation and insertion, cell scrambling, and converts the data

RLCD15

Abstract: 11-B 11-D DS26102 of bc 237 b E1 frame
Contextual Info: DS26102 16-Port TDM-to-ATM PHY www.maxim-ic.com GENERAL DESCRIPTION FEATURES On the transmit side, the DS26102 receives ATM cells from an ATM device through a UTOPIA II interface, provides cell buffering up to 4 cells , HEC generation and insertion, cell scrambling, and converts the data

DS377

Contextual Info: IDT 89EB-LOGAN-19 Evaluation Board Manual Evaluation Board: 18-692-001 February 2011 6024 Silver Creek Valley Road, San Jose, California 95138 Telephone: (800) 345-7015 • (408) 284-8200 • FAX: (408) 284-2775 Printed in U.S.A. 2011 Integrated Device Technology, Inc.

IR DATABOOK SCR

Abstract: cmos logic databook BTS 8800 COMCLOK 13.56 CON12 line output transformer for television Transformer te-e TTL databook TTL databook application CS61584A
Contextual Info: CS61584A Product Databook =CIRRUS LOGIC FEATURES • Dual T1/E1 Line Interface ■ 3.3 Volt and 5 Volt Versions D ual T1/E1 Line In terface ■ Crystalless Jitter Attenuator Meets European CTR 12 and ETSI ETS 300 011 Specifications ■ Matched Impedance Transmit Drivers

Contextual Info: CS61584A CS61584A Dual Dual T1/E1 T1/E1 Line Line Interface Interface Features – AT&T Publication 62411 – ETSI ETS 300 011, 300 233, CTR 12, TBR 13 l Dual T1/E1 Line Interface Volt and 5 Volt Versions l Crystal-less Jitter Attenuator Meets European CTR 12 and ETSI ETS 300 011

CS61584A

Contextual Info: CS61584A Product Technical Brief Reading and Writing Waveforms on the CS61584A The Arbitrary Waveform Generator AWG is a unique feature of Crystal LIU’s that allows the customization of the output waveform for non-standard terminations. The function of the AWG on the

TD38-1505A

Abstract: rneg2
Contextual Info: P R E L IM IN A R Y 8/ 11/97 A Cirrus Logic Company C S 6 1 5 8 4 A Dual T1/E1 Line Interface Features General Description • Dual T1/E1 Line Interface The CS61584A is a dual line interface for T1/E1 appli­ cations, designed for high-voiume cards where low

CON12

Abstract: CS61584A CS61584A-IL3 CS61584A-IL5 CS61584A-IQ3 CS61584A-IQ5 BIPOLAR MEMORY
Contextual Info: CS61584A Dual T1/E1 Line Interface Features – AT&T Publication 62411 – ETSI ETS 300 011, 300 233, CTR 12, TBR 13 l Dual T1/E1 Line Interface Volt and 5 Volt Versions l Crystalless Jitter Attenuator Meets European CTR 12 and ETSI ETS 300 011 Specifications

ASD 800 ASD 810

Abstract: LS 1017 TRANSFORMER BTS 8800 CON12 CS61584A CS61584A-IL5 CS61584A-IQ3 CS61584A-IQ5 BIPOLAR MEMORY RV-1 1k
Contextual Info: CS61584A CS61584A Dual Dual T1/E1 T1/E1 Line Line Interface Interface Features – AT&T Publication 62411 – ETSI ETS 300 011, 300 233, CTR 12, TBR 13 l Dual T1/E1 Line Interface Volt and 5 Volt Versions l Crystal-less Jitter Attenuator Meets European CTR 12 and ETSI ETS 300 011

max14574

Abstract: MAX1786 MAX1788 MAX8899 DS1849 MAX16908 MAX4967 DS3610 max17018 max13487
Contextual Info: Monitor Reports by Product: 1. Find the product of interest in the table below. Note the process and/or package for that product. 2. Use the "Back" button to return to the home page. 3. Select the process in the "Process Reliability" for the product of interest.

Contextual Info: Data Sheet AKU340 Analog MEMS Microphone Data Sheet AKU340 Analog MEMS Microphone Datasheet Part number s AKU340 Package type LGA, bottom port, metal lid Data sheet revision 1.0 Release date 4 June 2013 Document number DS26-1.0 AKU340 Data Sheet Notes Specifications are subject to change without notice.

cn/A/U 237 BG

Contextual Info: CS61584A = Product Databook CIRRUS LOGIC FEATURES • DualT1/E1 Line Interface ■ 3.3 Volt and 5 Volt Versions Dual T1/E1 Line Interface ■ Crystalless Jitter Attenuator Meets European CTR 12 and ETSI ETS 300 011 Specifications DESCRIPTION ■ Matched Impedance Transmit Drivers

Contextual Info: Semiconduc DS26S10 ^ j^ N a tio n a l or DS26S10 Quad Bus Transceiver General Description The D S 26S 10 is a quad Bus Transceiver consisting of 4 high speed bus drivers with open-collector outputs capable of sinking 100 mA at 0.8V and 4 high speed bus receivers.

AMI 52 732 V

Abstract: ACT 4060 ASH
Contextual Info: CS61584A Product Databook FEATURES n Dual T1/E1 Line Interface n 3.3 Volt and 5 Volt Versions Dual T1/E1 Line Interface n Crystalless Jitter Attenuator Meets European CTR 12 and ETSI ETS 300 011 Specifications DESCRIPTION n Matched Impedance Transmit Drivers