ECL NOT Search Results

Contextual Info: TNETA1545 DUAL DIFFERENTIAL PSEUDO-ECL TO ECL TRANSLATORS AND DUAL DIFFERENTIAL ECL TO PSEUDO-ECL TRANSLATORS SDNS005B - SEPTEMBER 1993 - REVISED OCTOBER 1995 • Dual ECL to Pseudo-ECL and Pseudo-ECL to ECL Translators • Single 5-V Power Supply • Advanced BiCMOS Technology

SG86A

Abstract: SG53A sg72a LVEP17 MC100ELxxx EP809 LVEL40 SLVS TR30 AND8020
Contextual Info: AN1568/D Interfacing Between LVDS and ECL Prepared by: Paul Lee Logic Applications Engineer ON Semiconductor http://onsemi.com APPLICATION NOTE ECL levels Today’s applications typically use ECL devices in the PECL mode. PECL Positive ECL is nothing more than

Contextual Info: MC10H604 MC100H604 MOTOROLA Product Preview REGISTERED HEX TTL TO ECL TRANSLATOR Registered Hex TTL/ECL Translator The MC1 OH/100H604 is a 6-bit, registered, dual supply TTL to ECL translator. The de­ vice features differential ECL outputs as well as a choice between either a differential ECL

10H645

Abstract: E211 MC10E111 MPC973 AN1405
Contextual Info: AN1405/D ECL Clock Distribution Techniques Prepared by Todd Pearson ECL Applications Engineering http://onsemi.com APPLICATION NOTE This application note provides information on system design using ECL logic technologies for reducing system clock skew over

CY101E383

Abstract: E383 R2170 ecl 84
Contextual Info: E383 CY101E383 ECL/TTL/ECL Translator and High-Speed Bus Driver Features • BiCMOS for optimum speed/power • High speed max. — 3.0 ns tPD TTL-to-ECL Functional Description The CY101E383 is a new-generation TTL-to-ECL and ECL-to-TTL logic level translator designed for high-perfor-

10H645

Abstract: AN1405 E211 MC10E111 MPC973
Contextual Info: AN1405 Application Note ECL Clock Distribution Techniques Prepared by Todd Pearson ECL Applications Engineering This application note provides information on system design using ECL logic technologies for reducing system clock skew over the alternative CMOS and TTL

10H645

Abstract: AN1405 DL140 E211 MC10E111 MPC973
Contextual Info: AN1405 Application Note ECL Clock Distribution Techniques Prepared by Todd Pearson ECL Applications Engineering This application note provides information on system design using ECL logic technologies for reducing system clock skew over the alternative CMOS and TTL

mb 3712

Contextual Info: SK10/100EL91W Triple PECL to ECL/LVECL and LVPECL to ECL/LVECL Translator HIGH-PERFORMANCE PRODUCTS Description Features The SK10/100EL91W is a triple PECL to ECL/LVECL and LVPECL to ECL/LVECL translator. It is fully compatible with MC100EL91 and MC100LVEL91. The

ecl 10K

Abstract: RCD Components E1001 E1004 E1008 E103 E105 SCHEMAT
Contextual Info: PRELIMINARY ECL DIGITAL DELAY LINES -5-41-5 - ECL 10K INTERFACED -5-41-5 - ECL 100K INTERFACED FEATURES TYPE E105 - ECL 10K 5 TAP Tap Delay nS 3 20 4 25 5 30 6 2X Total Delay Pulse Spacing 5X Total Delay -1.0V provided by open emitter ECL 10K gate

XEP56V

Abstract: SY100EP56VK4GTR MC100EP56DT MC100EP56DTR2 SY100EP56V SY100EP56VK4G SY100EP56VK4I SY100EP56VK4ITR
Contextual Info: ECL Pro 3.3V/5V PECL/ECL 3GHz DUAL DIFFERENTIAL 2:1 MULTIPLEXER Micrel, Inc. SY100EP56V ECL Pro™ SY100EP56V FEATURES • Dual, fully differential 2:1 PECL/ECL multiplexer ■ Guaranteed AC parameters over temperature/ voltage: • > 3GHz fMAX toggle

H604

Abstract: MC100H604 MC100H604FN MC10H604 MC10H604FN
Contextual Info: MC10H604, MC100H604 Registered Hex TTL to ECL Translator The MC10H/100H604 is a 6–bit, registered, dual supply TTL to ECL translator. The device features differential ECL outputs as well as a choice between either a differential ECL clock input or a TTL

marking Ed11

Contextual Info: PECL, ECL, LVDS Page 1 - 6 Pl tronics,. Inc. 19013 36th Ave. W, Suite H Lynnwood, WA 98036 USA Manufacturer of High Quality Frequency Control Products ED1145M ECL Series Full Size Metal Thru-Hole ECL Oscillator Differential or NonDifferential ECL Output without Enable/Disable

PLCC-28

Abstract: H604 MC100H604 MC10H604 MC10H604FN
Contextual Info: MC10H604, MC100H604 Registered Hex TTL to ECL Translator Description The MC10H/100H604 is a 6−bit, registered, dual supply TTL to ECL translator. The device features differential ECL outputs as well as a choice between either a differential ECL clock input or a TTL clock

XEP57V

Abstract: marking k4 XEP57
Contextual Info: ECL Pro 3.3V/5V PECL/ECL 3GHz DIFFERENTIAL 4:1 MULTIPLEXER Micrel ECL Pro™ SY100EP57V SY100EP57V FINAL FEATURES • Fully differential 4:1 PECL/ECL multiplexer ■ Guaranteed AC-parameters over temp/voltage: • > 3GHz Fmax toggle • < 220ps rise/fall Time

MC10EP58D

Abstract: MC10EP58DR2 SY100EP58V SY10EP58V SY10EP58VZI SY10EP58VZITR
Contextual Info: ECL Pro SY10EP58V ECL Pro™ SY100EP58V 3.3V/5V 3GHz PECL/ECL 2:1 MULTIPLEXER Micrel, Inc. SY10EP58V SY100EP58V FEATURES • 2:1 PECL/ECL multiplexer ■ Guaranteed AC–performance over temperature/voltage • >3GHz fMAX toggle • <200ps rise/fall time

EL91W

Abstract: 597v
Contextual Info: SK10/100EL91W Triple PECL to ECL/LVECL and LVPECL to ECL/LVECL Translator PRELIMINARY HIGH-PERFORMANCE PRODUCTS Description Features The SK10/100EL91W is a triple PECL to ECL/LVECL and LVPECL to ECL/LVECL translator. It is fully compatible with MC100EL91 and MC100LVEL91. The

XEP57V

Contextual Info: 3.3V/5V PECL/ECL 3GHz DIFFERENTIAL 4:1 MULTIPLEXER Micrel, Inc. ECL Pro SY100EP57V ECL Pro™ SY100EP57V FEATURES • Fully differential 4:1 PECL/ECL multiplexer ■ Guaranteed AC-parameters over temp/voltage: • > 3GHz Fmax toggle • < 220ps rise/fall Time

H604

Contextual Info: MC10H604, MC100H604 Registered Hex TTL to ECL Translator The MC10H/100H604 is a 6−bit, registered, dual supply TTL to ECL translator. The device features differential ECL outputs as well as a choice between either a differential ECL clock input or a TTL clock

Contextual Info: TIEPAL10016ET6C ECL-TO-TTLIMPACT-X" PAL TRANSLATOR CIRCUIT D3352, OCTOBER 1989 • ECL 100K Programmable Logic with ECL-to-TTL Translation JT PACKAGE TOP VIEW • ECL Control Inputs vcc[ '[ l[ l[ l[ l[ '[ '[ • 3-State TTL Outputs • IMPACT-X“ Process with Reliable

F100K ECL 300 series and design guide

Abstract: F100K ECL book F100K AN-780
Contextual Info: Fairchild Semiconductor Application Note May 1991 Revised February 2004 Operating ECL from a Single Positive Supply Introduction ECL is normally specified for operation with a negative VEE power source and a negative VTT termination supply. This is the optimum operating configuration for ECL but not the

XEL25

Abstract: code Z8
Contextual Info: DIFFERENTIAL ECL-to-TTL TRANSLATOR FEATURES • ■ ■ ■ ■ DESCRIPTION 2.6ns typical propagation delay Differential ECL inputs 24mA TTL outputs Flow-through pinouts Available in 8-pin SOIC package The SY100ELT25 is a differential ECL-to-TTL translator. Because ECL levels are used, a +5V, –5.2V

CML ECL termination

Abstract: dj rm RJ12 RJ22
Contextual Info: I/O Structures and Jitter Presentation 1 RELATIVE SIGNAL SWINGS AND LEVELS PECL 4V “5V ECL” CML 3.3V 3V CML (2.5V) LVPECL 2V LVPECL LVDS -1V -2V CML (1.2V) “3V ECL” 1V 0V CML (1.8V) Referenced to Ground “2.5V ECL” ECL Older Technology - Rarely seen

F100K ECL 300 series and design guide

Abstract: ESD diode ,F100K ECL book AN-780 F100K F100K ECL book
Contextual Info: Fairchild Semiconductor Application Note May 1991 Revised May 2000 Operating ECL from a Single Positive Supply INTRODUCTION ECL is normally specified for operation with a negative VEE power source and a negative VTT termination supply. This is the optimum operating configuration for ECL but not the

Contextual Info: 3.3V/5V 2.5GHz PECL/ECL 1:4 FANOUT BUFFER WITH 2:1 INPUT MUX Micrel, Inc. ECL Pro SY100EP15V ECL Pro™ SY100EP15V FEATURES • High-speed 1:4 PECL/ECL fanout buffer ■ 2:1 multiplexer input ■ Guaranteed AC parameters over temp/voltage: • > 2.5GHz fMAX toggle