ECL VIDEO Search Results

EIA-644

Abstract: PECL-to-SN64LVDS33
Contextual Info: Interface Data Transmission Texas Instruments Incorporated The SN65LVDS33/34 as an ECL-to-LVTTL converter By Chris Sterzik Applications Specialist, Interface Products Introduction Figure 1. ECL characteristic load Emitter-coupled logic (ECL) has often been the physical

Contextual Info: DP8480A DP8480A 10k ECL to TTL Level Translator with Latch Literature Number: SNOSBN8A DP8480A 10k ECL to TTL Level Translator with Latch General Description Features This circuit translates ECL input levels to TTL output levels and provides a fall-through latch The TRI-STATE outputs

Contextual Info: DP8482A DP8482A 100k ECL to TTL Level Translator with Latch Literature Number: SNOSBO0A DP8482A 100k ECL to TTL Level Translator with Latch General Description Features This circuit translates ECL input levels to TTL output levels and provides a fall-through latch The TRI-STATE outputs

Contextual Info: 100329 100329 Low Power Octal ECL/TTL Bidirectional Translator with Register Literature Number: SNOS122A 100329 Low Power Octal ECL/TTL Bidirectional Translator with Register General Description The 100329 is an octal registered bidirectional translator designed to convert TTL logic levels to 100K ECL logic levels

Contextual Info: 100324 100324 Low Power Hex TTL-to-ECL Translator Literature Number: SNOS128A 100324 Low Power Hex TTL-to-ECL Translator General Description Features The 100324 is a hex translator, designed to convert TTL logic levels to 100K ECL logic levels. The inputs are compatible

F100K ECL 300 series and design guide

Abstract: F100K ECL book F100K AN-780
Contextual Info: Fairchild Semiconductor Application Note May 1991 Revised February 2004 Operating ECL from a Single Positive Supply Introduction ECL is normally specified for operation with a negative VEE power source and a negative VTT termination supply. This is the optimum operating configuration for ECL but not the

DP8481

Contextual Info: DP8481 DP8481 TTL to 10k ECL Level Translator with Latch Literature Number: SNOSBN9A DP8481 TTL to 10k ECL Level Translator with Latch General Description Features This circuit translates TTL input levels to ECL output levels and provides a fall-through latch The outputs are gated with

Contextual Info: DP8483 DP8483 TTL to 100k ECL Level Translator with Latch Literature Number: SNOSBO1A DP8483 TTL to 100k ECL Level Translator with Latch General Description Features This circuit translates TTL input levels to ECL output levels and provides a fall-through latch The outputs are gated with

F100K ECL 300 series and design guide

Abstract: ESD diode ,F100K ECL book AN-780 F100K F100K ECL book
Contextual Info: Fairchild Semiconductor Application Note May 1991 Revised May 2000 Operating ECL from a Single Positive Supply INTRODUCTION ECL is normally specified for operation with a negative VEE power source and a negative VTT termination supply. This is the optimum operating configuration for ECL but not the

F100K ECL 300 series and design guide

Abstract: F100K ECL book AN-780 F100K300 ,F100K ECL book F100K F100K ECL 300 series databook and design guide
Contextual Info: Fairchild Semiconductor Application Note 780 May 1991 INTRODUCTION ECL is normally specified for operation with a negative VEE power source and a negative VTT termination supply. This is the optimum operating configuration for ECL but not the only one. Operating ECL from a positive VCC supply is a practical

B199 RF transistor datasheet

Abstract: F100K ECL 300 series and design guide AN-780 C1995 F100K 7474-ttl AN-780 national F100K ECL book
Contextual Info: National Semiconductor Application Note 780 John Davis May 1991 INTRODUCTION ECL is normally specified for operation with a negative VEE power source and a negative VTT termination supply This is the optimum operating configuration for ECL but not the only one Operating ECL from a positive VCC supply is a

uA 741 IC pin configuration

Abstract: internal circuit diagram of IC 741 ic 741 datasheet internal diagram of 741 IC uA 741 OF IC 741 pin diagram of ic 741 uA 741 IC shift register ic pdf of 741 ic
Contextual Info: VITESSE SEMICONDUCTOR CORPORATION Preliminary Datasheet 500 Mb/s Video Shift Register IC VSC6424 Features • ECL and TTL I/Os: ECL for high-speed interface, TTL for low-speed interface • Multiplex or Demultiplex Operation • Selectable Shift Register Length

Contextual Info: ECL OSCILLATORS OEN/OEP SERIES 14 PIN ECL CLOCK OSCILLATORS APPLICATIONS: VIDEO, HIGH SPEED LOGIC Typical Electrical Characteristics Frequency Range : 30.0 MHz to 250.0 MHz Supply Voltage : OEN = -5.2V OEP = 5.0V Output Symmetry : 40% Min- 60% Max Rise Time TR

ICD2062A

Abstract: ICD2062B
Contextual Info: ICD2062B Dual Programmable ECL/TTL Clock Generator to produce the following: a 10 K compatible complementary ECL output signal for highĆspeed video RAMDACs, a highĆspeed TTL output signal for video RAMs and system logic operation, and the requisite load, control, and clock

MPD1750-04

Abstract: SC9103-07 ttl ecl
Contextual Info: Monolithic Multi-Throw Driver Chips 03Alpha MPD1750-04 Features • 4 ns Video Switching Time ■ Low in Band Noise: -5 0 dBm at 1 GHz ■ True Differential Inputs ■ Compatible with TTL, ECL, and CMOS to 5.0V ■ Internal Referenced for TTL, ECL ■ Inverting, Non-Inverting

Contextual Info: SN65EL16 www.ti.com. SLLS921 – NOVEMBER 2008 5-V ECL Differential Receiver

Contextual Info: SN65EL16 www.ti.com. SLLS921 – NOVEMBER 2008 5-V ECL Differential Receiver

T0404

Contextual Info: SN65EL16 www.ti.com. SLLS921 – NOVEMBER 2008 5-V ECL Differential Receiver

SN65LVDS108

Abstract: SN65LVDS116
Contextual Info: Interface Data Transmission Texas Instruments Incorporated Power consumption of LVPECL and LVDS By Chris Sterzik Applications Specialist, Interface Products Introduction Figure 1. Models of ECL and LVDS output drivers and terminations Single-ended emitter-coupled logic (ECL) has

T0404

Abstract: T0402 capacitor MC100EL16 MC10EL16 SN65EL11 SN65EL16 SN65EL16D SN65EL16DGK
Contextual Info: SN65EL16 www.ti.com. SLLS921 – NOVEMBER 2008 5-V ECL Differential Receiver

Contextual Info: SN65EL16 www.ti.com. SLLS921 – NOVEMBER 2008 5-V ECL Differential Receiver

Contextual Info: SN65LVEL11 www.ti.com. SLLS927 – DECEMBER 2008 3.3 V ECL 1:2 Fanout Buffer

lm385 IC circuit diagram

Abstract: MC10324 eia 343 LM385/MAX4135/MAX4136/MAX4137/LM385/MAX4135/MAX4136/MAX4137/2n7000 equivalent
Contextual Info: MOTOROLA SEMICONDUCTOR MC10324 TECHNICAL DATA Advance Information 8-Bit Video DAC with ECL Inputs 8-BIT VIDEO DAC with ECL INPUTS The MC10324 is a 40 MegaSample Per Second MSPS 8-bit Video DAC capable of directly driving a 75 S2 cable, with appropriate terminations, to EIA-170 and EIA-343-A video levels. The logic inputs

Contextual Info: Telecommunications Products Product Summary Product Family Description . - :• Featuret ■ . .■ . . Serial Data up to 2.5 Gb/s ECL 1OOK Compatible Parallel Data I/O Single ECL Power Supply: VEE = -5.2 V 1.5 W Pcwer Dissipation Typ. 28-pin Ceramic LDCC Package