EF40 Search Results

HEF4002BP

Abstract: HEF4002BD HEF4002B HEF4002BT
Contextual Info: EF4002B gates DUAL 4-INPUT NOR GATE The H EF4002B provides the positive dual 4-input NOR function. The outputs are fully buffered for highest noise im m unity and pattern insensitivity o f output impedance. fcU ïïlÆ J^ ïïU F L Ji^ VpD 02 D 0, ^8 h ^6

hef4060BP

Abstract: HEF4060 pin configuration of hef4060bp HEF4060BT HEF4060B MSI HEF4060B
Contextual Info: EF4060B MSI 14-STAGE RIPPLE-CARRY BINARY COUNTER/DIVIDER AND OSCILLATOR The H EF4060B is a 14-stage rip ple-ca rry b in a ry c o u n te r/d iv id e r and o scilla to r w ith three oscilla to r term inals RS, R j q and C-pc ' ten buffered o u tp u ts (O3 to Og and 0 -| -\ to O 13) and an overriding

HEF4002B

Abstract: hef4002
Contextual Info: EF4002B gates DUAL 4-INPUT NOR GATE The H EF4002B provides the positive dual 4-input NOR function. The outputs are fuliy buffered for highest noise im m unity and pattern insensitivity o f output impedance. 2 I1 3 I*!"*— u r -— 4 5 9 15 10 11 12 E= 0,

EF40

Contextual Info: page 1 2 3 4 5 6 7 EF40 sheet 1 2 3 4 A B FP date 1954.06.06 1954.06.06 1953.11.11 1953.11.11 1948.10.22 1948.10.22 1999.06.28

Contextual Info: EF4068B gates 8-INPUT NAND GATE The H EF4068B provides the 8-input N A N D function. The outputs are fully buffered for highest noise imm unity and pattern insensitivity of output impedance. a o >° lg I5 li n .c . nc Vs s EF4068B 3 n .c . I7 I0 I, Ij I3

HEF40146

Abstract: CP1015
Contextual Info: EF40146 MSI 8-BIT STATIC SHIFT REGISTER The H EF4014B is a fully synchronous edge-triggered 8 -bit static shift register w ith eight synchronous parallel inputs Pq to P7 , a synchronous serial data input (D s), a synchronous parallel enable input (PE), a LOW to H IG H edge-triggered clock input (CP) and buffered parallel outputs from the last three

KS 4558

Abstract: ef40 pour 4558 Philips 4558 ef 40 f 4558 RS 4558 TRIODE itl hfi1
Contextual Info: PHILIPS EF40 PENTODE fer use as A.F. amplifier PENTHODE pour Utilisation en amplificatrice B.F. PSNÏODE zur Verwendung als NF-Verstärker Heating : indirect by A.C. or D.C.; series or parallel supply Chauffage: indirect par C.A. ou C.C.; Vf = 6,3 V alimentation- parallèle ou

Contextual Info: 40x40x20 mm 6.3~10.8 CFM Specifications Bearing Model 2BALL Sleeve Rating Voltage Power Current Power Consumption Speed Air Flow Static Pressure Noise Weight Curve VDC (mA) (WATTS) (RPM) (CFM) (Inch-H 2O) (dB(A) (g) EF40201BX-000U-A99 12 53 0.64 6800 10.8

hef4023bp

Contextual Info: H EF4023B gates TRIPLE 3-INPUT NAND GATE The H E F 4023B provides th e positive trip le 3 -in p u t N A N D fu n c tio n . The o u tp u ts are fu lly buffered fo r highest noise im m u n ity and p a ttern in se n sitivity o f o u tp u t impedance. Vdo I 9

HEF4013BP

Abstract: HEF4013 HEF4013BT hef4013b HEF4013BD 7Z69524
Contextual Info: H EF4013B flip-flops DUAL D -TY P E FLIP-FLOP The EF4013B is a dual D-type flip -flo p which features independent set direct S q , clear direct (C q ), clock inputs (CP) and outputs (0,C5). Data is accepted when CP is LOW and transferred to the ou tput on

HEF4093BP

Abstract: HEF4093BP applications Hef4093bt hef4093
Contextual Info: y v QUADRUPLE 2-INPUT NAND SCHMITT TRIGGER The H EF4093B consists o f four Schmitt-trigger circuits. Each circuit functions as a two-input N A N D gate with Schmitt-trigger action on both inputs. The gate switches at different points for positive and negative-going signals. The difference between the positive voltage Vp and the negative voltage

DR 25 specifications

Contextual Info: EF40245B buffar* OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS The H EF40245B is an octal bus transmitter/receiver designed for 8 -line asynchronous, 2-way data communication between data buses. It features output stages with high current output capability suitable for driving highly capacitive loads.

Contextual Info: EF4073B gates J K. TRIPLE 3-INPUT AND GATE The H EF4073B provides the positive triple 3-input A N D function. The outpu :s are fully buffered for highest noise im m unity and pattern insensitivity of output impedance. ra_fïïUïïl_FTl_F5U9U?L VdO J 9 D

4049bt

Abstract: 4049bp
Contextual Info: IN TE G R A TE D CIRCUITS EF4049B buffers HEX inverting buffers Product specification File under Integrated C ircuits, IC04 Philips Semiconductors January 1995 PHILIPS PHILIPS Philips S e m ico nd uctors P ro d u c t specification H EF4049B H E X inverting buffers

HEF40

Contextual Info: EF40S3B MSI 4-BIT UP/DOWN BNARY COUNTER The H EF40193B is a 4-bit synchronous up/down binary counter. The counter has a count-up clock input C P y , a count-down clock input (CPq), an asynchronous parallel load input (PL), four parallel data inputs (Po to P3 ), an asynchronous master reset input (M R ), four counter outputs (Oq to 0 3 ), an

HEF40175BP

Contextual Info: EF40175B MSI QUADRUPLE D-TYPE FLIP-FLOP The H EF40175B is a quadruple edge-triggered D-type flip-flop with four data inputs Do to D3 , a clock input (CP), an overriding asynchronous master reset input (M ff), four buffered outputs (0 ( ) to O3 ), and four complementary buffered outputs (Oo to O3 ). Information on Dp to D3 is transferred to

HEF4025

Contextual Info: EF4025B gates TRIPLE 3-INPUT NOR GATE The H EF4025B provides the positive triple 3-input NOR function. The outputs are fully buffered for highest noise imm unity and pattern insensitivity of output impedance. 3 It Vq d I9 3 I7 O3 O2 I EF4025B I5 9 U Lu'"UJ

EF400

Contextual Info: EF4007UB gates DUAL COMPLEMENTARY PAIR AND INVERTER The H EF40Q 7U B is a dual complementary pair and an inverter with access to each device. It has three n-channel and three p-channel enhancement mode M O S transistors. rajnLJiUïïLJÎôUilJTÎ, VDD D p i D n /P3 Sp3

SRG8 -led

Abstract: SRG8 Multiplexer SRG4 4046 vco HEF4017 HEF4009 HEF4751V EF4016 HEF4053 pll 4046
Contextual Info: FUNCTIONAL DIAGRAMS/ IEC SYM BOLS H EF4 0 0 0 B Dual 3-input NO R gate and inverter. H E F4 0 0 1 U B H EF4001B 3 k yÀ ’ 2 171 V " 5 3 > ^ 6 10 — 3) V 1 h Quadruple 2-input N O R gate. 8 9 3) y * . 11. i Quadruple 2-input N O R gate; unbuffered. H EF4 0 0 2 B

HEF4068B

Abstract: HEF4068BD HEF4068BP HEF4068BT
Contextual Info: EF4068B gates 8-INPUT NAND GATE The H EF4068B provides the 8-input N A N D function. The outputs are fully buffered for highest noise im m unity and pattern insensitivity of output impedance. t fcU R JîlJïïLJ5U ¥lJ¥L D n.c. h ^6 '5 *4 n -c - H EF4068B

HEF4046

Abstract: HEF4046BT ECC90 HEF4046B MSI HEF4046BP
Contextual Info: EF4046B M SI PHASE-LOCKED LOOP The H EF40 46 B is a phase-locked loop circuit that consists of a linear voltage controlled oscillator V C O and two different phase comparators with a common signal input amplifier and a common comparator input. A 7 V regulator (zener) diode is provided for supply voltage regulation if necessary.

HEF4018BT

Abstract: HEF4018B
Contextual Info: EF4018B MSI PRESETTABLE DIVIDE-BY-N COUNTER The H EF4018B is a 5-stage Johnson counter with a clock input CP , a data input (D ), an asynchro­ nous parallel load input (PL), five parallel inputs (Pq to P4 ), five active LOW buffered outputs (Oo to O 4 ), and an overriding asynchronous master reset input (M R ).

HEF4082BP

Abstract: 15-1500F
Contextual Info: H EF4082B gates DUAL 4-INPUT AND GATE The H E F 4082B provides the positive dual 4-input A N D function. The outputs are fully buffered for highest noise im m unity and pattern insensitivity of output impedance. ^O ^UTzUrTUiölJTU^l VDD O 2 3 ¡8 ^6 I7 15

HEF40

Abstract: HEF4043BP
Contextual Info: H EF4043B MSI QUADRUPLE R/S LATCH WITH 3-STATE OUTPUTS T he H E F 4043B is a quadruple R/S latch w ith 3-state o u tp u ts w ith a com m on o u tp u t enable in p u t EO . Each latch has an active H IG H set in p u t (Sg to S3 ), an active H IG H reset in p u t (R q to R3 ) and