EP1830 JEDEC Search Results

EP1830 JEDEC Result Highlights (5)

Part	ECAD Model	Manufacturer	Description	Download	Buy
TMP139AIYAHR		Texas Instruments	JEDEC DDR5 temperature sensor with 0.5 °C accuracy 6-DSBGA -40 to 125
SN74SSQEA32882ZALR		Texas Instruments	JEDEC SSTE32882 Compliant 28-Bit to 56-Bit Registered Buffer with Address-Parity Test 176-NFBGA 0 to 85
SN74SSQE32882ZALR		Texas Instruments	JEDEC SSTE32882 Compliant 28-Bit to 56-Bit Registered Buffer with Address-Parity Test 176-NFBGA 0 to 85
SN74SSQEB32882ZALR		Texas Instruments	JEDEC SSTE32882 Compliant 28-Bit to 56-Bit Registered Buffer with Address-Parity Test 176-NFBGA 0 to 85
SN74SSQEC32882ZALR		Texas Instruments	JEDEC SSTE32882 Compliant Low Power 28-Bit to 56-Bit Registered Buffer with Address-Parity Test 176-NFBGA 0 to 85

EP1830 JEDEC Datasheets Context Search

Catalog Datasheet	MFG & Type	PDF	Document Tags
Untitled Abstract: No abstract text available Text: EP1830 EPLD Features □ □ General Description Altera's EP1830 Erasable Programmable Logic Device EPLD is a fast, low-power version of the EP1810 device. The EP1830 can implement four 12-bit counters at up to 50 MHz and typically consumes 20 mA when operating at 1 MHz. The EP1830 EPLD is available in OTP plastic 68-pin	OCR Scan	PDF	EP1830 EP1810 12-bit 68-pin EP1830-20, EP1830-25,
Altera EP1810 Abstract: No abstract text available Text: ALTERA CORP 47E D • 05*15372 DQ0211b 376 ■ ALT T ^ to -o / EP1810 EPLD s A N b [m □ □ □ □ □ □ □ □ □ □ High-density replacement for TTL and 74HC High-performance 48-macrocell EPLD with tPD = 20 ns and counter frequencies up to 50 MHz	OCR Scan	PDF	000211b EP1810 48-Macrocell EP1830-20, EP1830-25, EP1830-30 EP1830-25 EP1830 Altera EP1810
EP1830 Abstract: EP1810 jedec 74HC EP1810 EP18302 EP1830 jedec Text: EP1810 EPLDs High-Performance 48-Macrocell Devices Data Sheet September 1991, ver. 2 Features □ □ □ □ □ □ □ Q General Description The EP1810 Erasable Programmable Logic Devices EPLDs offer LSI density,TTL-equivalentspeed, and low power consumption. Each EPLD can	OCR Scan	PDF	EP1810 48-Macrocell EP1830-20, EP1830-25, EP1830-30 EP1830-25 EP1830 EP1810 jedec 74HC EP18302 EP1830 jedec
Untitled Abstract: No abstract text available Text: EP1800-Series EPLDs /an ù rü R*A\ Data Sheet October 1990, ver. 1 Features □ □ □ □ □ □ □ □ □ □ □ □ General Description High-Performance 48-Macrocell Devices Erasable, user-configurable LSI circuit capable of im plem enting up to 2,100 equivalent gates of conventional and custom logic	OCR Scan	PDF	EP1800-Series 48-Macrocell 1830tj
Untitled Abstract: No abstract text available Text: ANbrt r*a\ EP1810 EPLDs High-Performance 48-Macrocell Devices September 1991, ver. 2 Features Data Sheet □ □ □ □ □ □ □ □ □ □ General Description tPD The EP1810 Erasable Program m able Logic Devices E P L D s offer L S I density, TTL-equivalent speed, and low power consumption. Each E P L D can	OCR Scan	PDF	EP1810 48-Macrocell programEP1810
Untitled Abstract: No abstract text available Text: EP1810 EPLDs High-Performance 48-Macrocell Devices Data Sheet September 1991, ver. 2 Features □ □ □ □ □ □ □ □ □ □ General Description The EP1810 Erasable Program m able Logic D evices EPLDs offer LSI density, 1"1 L-equivalent speed, and low pow er consumption. Each EPLD can	OCR Scan	PDF	EP1810 48-Macrocell 68-pin
Untitled Abstract: No abstract text available Text: EP1810T EPLD Features □ □ □ □ General Description Altera's EP1810T Erasable Programmable Logic Device EPLD is a lowcost, high-performance version of the EP1810 device. This EPLD operates in a turbo mode that is optimized for high-speed applications. The Turbo	OCR Scan	PDF	EP1810T EP1810 68-pin EP1810-20T, EP1810-25T, EP1810-35T
Untitled Abstract: No abstract text available Text: EP1810 EPLD Features General Description The EP1810 Erasable Programmable Logic Device EPLD offers LSI density, TTL-equivalent speed, and low power consumption. It is available in 68-pin windowed ceramic and OTP plastic J-lead chip carrier and windowed ceramic PGA packages. See Figure 7.	OCR Scan	PDF	EP1810 68-pin EP1810-20 EP1810-25
Untitled Abstract: No abstract text available Text: EP1810 EPLD Features □ Ü □ J General Description The EP1810 Erasable Programmable Logic Device E P L D offers L S I density, TTL-equivalent speed, and low power consumption. It is available in 68-pin w ind ow ed ceramic and O T P plastic j-lead chip carrier and w indow ed	OCR Scan	PDF	EP1810 48-macrocell EP1810T EP1830 68-pin EP1810-20
22CV10AP Abstract: 22cv10 nte quick cross ict peel 18CV8J palce programmer schematic blackjack vhdl code PA7140J-20 INTEL PLD910 PALCE610 Text: Data Book General Information PEEL Arrays PEEL Devices Special Products and Services Development Tools Application Notes and Reports Package Information PLACE Users Manual_ Introduction to PLACE PLACE Installation Getting Started with PLACE Operation Reference Guide	OCR Scan	PDF
programming manual EPLD EPS448 Abstract: Altera EPM5128 EPM7064-12 leap u1 EP-900910 PLE3-12a tcl tv circuit altera eplds EP610 "pin compatible" ALTERA MAX 5000 Text: Data Book TENTH ANNIVERSARY A Decade of Leadership A u g u s t 1993 Data Book August 1993 A-DB-0793-01 Altera, MAX, and M A X+PLUS are registered trademarks of Altera Corporation. The following, among others, are trademarks of Altera Corporation: AHDL, M AX+PLUS II, PL-ASAP2, PLDS-HPS, PLS-ADV, PLS-ES, PLS-FLEX8, PLS-FLEX8/H P, PLS-FLEX8/SN , PLS-HPS, PLS-STD, PLS-W S/H P,	OCR Scan	PDF	-DB-0793-01 EP330, EP610, EP610A, EP610T, EP910, EP910A, EP910T, EP1810, EP1810T, programming manual EPLD EPS448 Altera EPM5128 EPM7064-12 leap u1 EP-900910 PLE3-12a tcl tv circuit altera eplds EP610 "pin compatible" ALTERA MAX 5000