EP9101 Search Results

EP-912

Abstract: EP9100
Contextual Info: SMD 28 Pin 5 Tap TTL Compatible Active Delay Lines J-Lead P/N Delays are ±5% or ±2 nS Tap Total 5, 10, 15, 20 6, 12, 18, 24 7 ,1 4,2 1 ,2 8 8, 16,24,32 9, 18, 27,36 10,20, 30,40 12, 24, 36, 48 15,30, 45,60 EP9100 EP9101 EP9102 EP9103 EP9104 EP9105 EP9106

Contextual Info: SMD 28 Pin 5 Tap TTL Compatible Active Delay Lines J-Lead P/N Delays are ±5% or ±2 nSt Tap Total 5, 10, 15, 20 6 , 12, 18, 24 7 ,1 4 ,2 1 ,2 8 8 ,1 6 ,2 4 , 32 9, 18, 27, 36 10, 20, 30, 40 12, 24, 36, 48 15, 30, 45, 60 EP9100 EP9101 EP9102 EP9103 EP9104

Contextual Info: SMD 28 Pin 5 Tap TTL Compatible Active Delay Lines Delays are ±5% or ±2 nS Tap Total 25 30 35 40 45 50 60 75 5 ,1 0,1 5 ,2 0 6,12,18, 24 7,1 4,2 1 ,2 8 8,16, 24, 32 9,18, 27,36 10,20,30,40 12,24, 36,48 15,30,45,60 Gull-Wing P/N J-Lead P/N EP9100 EP9101 EP9102

EP9100

Abstract: EP9122 EP9108 EP9109 EP9110 EP9111 EP9112 EP9113 EP9114 EP9129
Contextual Info: 28 Pin SMD 5 Tap TTL Compatible Active Delay Lines ELECTRONICS INC. EP9100 to EP9129 & EP9100-RC to EP9129-RC Add “-RC” after part number for RoHS Compliant J-Lead Part Number EP9100 -RC EP9101(-RC) EP9102(-RC) EP9103(-RC) EP9104(-RC) EP9105(-RC) EP9106(-RC)

EP9122

Abstract: circuit ep9100 smd 57b EP9100 EP9101 EP9102 EP9108 EP9109 EP9110 EP9115
Contextual Info: SMD 28 Pin 5 Tap TTL Compatible Active Delay Lines Delays are ±5% or +2 nSt Tap Total 5, 10, 15, 20 6, 12, 18, 24 7, 14, 21, 28 8, 16, 24, 32 9, 18, 27, 36 10, 20, 30, 40 12, 24, 36, 48 15, 30, 45, 60 J-Lead P/N 25 30 35 40 45 50 60 75 t Whichever is greater.

EP610-25

Abstract: programmer EPLD EP1810 EP610 EP910 ep910 programmer QLCC 24 EP6101-10
Contextual Info: Classic E P L D F a m ily Ja n u a ry 1098, ve r 4 Features Data Sheet • ■ ■ ■ ■ ■ ■ ■ ■ ■ C om plete device fam ily w ith logic densities o f 300 to 9 X usable gates (see Table 1) D evice e ra su re an d reprogram m ing w ith advanced, non-volatile

EP910

Abstract: altera EP910
Contextual Info: EP910 EPLD Features • ■ ■ ■ ■ ■ High-performance, 24-macrocell Classic EPLD Combinatorial speeds with tPD as low as 12 ns Counter frequencies of up to 100 MHz Pipelined data rates of up to 100 MHz Programmable I/O architecture with up to 36 inputs or 24 outputs

P6102

Abstract: EP6101-10
Contextual Info: Classic EPLD Family J a n u ary 1998. v er. J Features Data S h e e t • ■ ■ ■ ■ ■ ■ ■ ■ ■ Complete device family w ith logic densities of 300 to 900 usable gates see Table 1 Device erasure and reprogram m ing w ith advanced, non-volatile

EP9122

Abstract: smd 57b EP9100 EP9101 EP9102 EP9108 EP9109 EP9110 EP9115 EP9116
Contextual Info: SMD 28 Pin 5 Tap TTL Compatible Active Delay Lines Delays are ±5% or +2 nSt Tap Total 5, 10, 15, 20 6, 12, 18, 24 7, 14, 21, 28 8, 16, 24, 32 9, 18, 27, 36 10, 20, 30, 40 12, 24, 36, 48 15, 30, 45, 60 J-Lead P/N 25 30 35 40 45 50 60 75 t Whichever is greater.

Contextual Info: SMD 28 Pin 5 Tap TTL Compatible Active Delay Lines Delays are ±5% or ±2 nS† Tap Total 5, 10, 15, 20 6, 12, 18, 24 7, 14, 21, 28 8, 16, 24, 32 9, 18, 27, 36 10, 20, 30, 40 12, 24, 36, 48 15, 30, 45, 60 J-Lead P/N 25 30 35 40 45 50 60 75 †Whichever is greater.

TD 265 N 600 KOC

Abstract: core i5 520 Scans-049 camtex trays sii Product Catalog EPM9560 film hot BT 342 project TIL Display 7160S
Contextual Info: 1996 Data Book Data Book June 1996 A-DB-0696-01 Altera, MAX, M A X+PLUS, FLEX, FLEX 10K, FLEX 8000, FLEX 8000A, MAX 9000, MAX 7000, MAX 7000E, MAX 7000S, FLASHlogic, MAX 5000, Classic, M AX+PLUS II, PL-ASAP2, PLDshell Plus, FastTrack, AHDL, MPLD, Turbo Bit, BitBlaster, PENGN, RIPP 10, PLS-ES, ClockLock, ClockBoost,

EP610

Abstract: ep910 programmer TI EP610 EP610-25 EP1810 EP910 ALTERA MAX 5000 programming EP6101-10
Contextual Info: Classic EPLD Family January 1998. ver. 4 Features Data Sheet • ■ ■ ■ ■ ■ ■ ■ ■ ■ Complete device family w ith logic densities of 300 to 900 usable gates see Fable 1 Device erasure and reprogram m ing w ith advanced, non-volatile EPROM configuration elements

Contextual Info: SMD 28 Pin 5 Tap TTL Compatible Active Delay Lines - - 5, 10, 15,20 6, 12, 18, 24 7, 14, 21,28 8,16, 24, 32 9, 18, 27, 36 10, 20, 30, 40 12, 24,36, 48 15, 30,45, 60 Gull-Wing P/N J-Lead P/N Delays are ±5% or ±2 nS

Contextual Info: SMD 28 Pin 5 Tap TTL Compatible Active Delay Lines Delays are ±5% or ±2 n S f Tap Total I I 25 30 35 40 45 50 60 75 5, 10, 15, 20 6, 12, 18, 24 7 ,1 4 ,2 1 ,2 8 8, 16, 24, 32 9, 18, 27, 36 10, 20, 30, 40 12, 24, 36, 48 15, 30, 45,60 t Whichever is greater.

P9101

Abstract: 3721d
Contextual Info: EP910 E P LD Features • ■ ■ ■ ■ ■ High-performance, 24-macrocell Classic EPLD Combinatorial speeds with tPD as fast as 12 ns Counter frequencies of up to 76.9 MHz Pipelined data rates of up to 125 MHz Programmable I/O architecture with up to 36 inputs or 24 outputs

altera ep900i

Abstract: IC MSI ADDER
Contextual Info: EP910 EPLD Features High-performance, 24-macrocell Classic EPLD Combinatorial speeds with tPD as low as 12 ns Counter frequencies of up to 76.9 MHz Pipelined data rates of up to 125 MHz Programmable I/O architecture with up to 36 inputs or 24 outputs EP910, EP910I, and EP900I devices that are pin-, function, and

altera EP9101

Abstract: ALTERA MAX 5000 programming altera ep910i
Contextual Info: E P 9 1 0 E P LD Features • ■ ■ ■ ■ ■ High-performance, 24-macrocell Classic EPLD Combinatorial speeds with tPD as fast as 12 ns Counter frequencies of up to 76.9 MHz Pipelined data rates of up to 125 MHz Programmable I/O architecture with up to 36 inputs or 24 outputs

EP9122

Abstract: EP9100 EP9101 EP9102 EP9103 EP9104 EP9105 EP9106 EP9107 EP9115
Contextual Info: SMD 28 Pin 5 Tap TTL Compatible Active Delay Lines Delays are ±5% or ±2 nS† Tap Total 5, 10, 15, 20 6, 12, 18, 24 7, 14, 21, 28 8, 16, 24, 32 9, 18, 27, 36 10, 20, 30, 40 12, 24, 36, 48 15, 30, 45, 60 J-Lead P/N 25 30 35 40 45 50 60 75 †Whichever is greater.

altera EP9101

Contextual Info: EP910EPLD Features • ■ ■ ■ ■ ■ High-performance, 24-macrocell Classic EPLD - Combinatorial speeds with t P D as fast as 12 ns Counter frequencies of up to 76.9 MHz Pipelined data rates of up to 125 MHz Programmable I/O architecture with up to 36 inputs or 24 outputs

altera EP910I

Abstract: EP910-T EP910i EP910 Altera Classic EPLDs
Contextual Info: E P 910 E P L D Features • ■ ■ ■ ■ ■ High-performance, 24-macrocell Classic EPLD Combinatorial speeds with tPD as low as 12 ns Counter frequencies of up to 100 MHz Pipelined data rates of up to 100 MHz Programmable I/O architecture with up to 36 inputs or 24 outputs

smd J225

Abstract: J225 EP9122 J2-25 EP9101
Contextual Info: SMD 28 Pin 5 Tap TTL Compatible Active Delay Lines J-Lead P/N Delays are ±5% or ±2 nSt Tap Total 5, 10, 15, 20 6, 12, 18, 24 7, 14, 21, 28 8, 16, 24, 32 9, 18, 27, 36 10, 20, 30, 40 12, 24, 36, 48 15, 30, 45, 60 t Whichever is greater. Gull-Wing P/N EP9100