F AX 1331 Search Results

MOR01W

Contextual Info: ROYALOHM Metal Oxide Film Fixed Resistors Performance Specification Tem perature C oefficient ±350PPM /°C Short Tim e Overload Normal size: ± 1.0% + 0.05Q M ax, with no evidence o f mechanical damage. Small size: +(2.0% + 0.05i2)M ax, with no evidence o f mechanical damage.

F1H16

Abstract: EPM 5192 epm5192 MSI MS-5 IC LM 384 gn
Contextual Info: EPM 5192 EPLD F e a tu re s • High-density, 192 macrocell, general-purpose M AX 5000 EPLD, easily integrating com plete logic boards into a single package High-speed m ulti-LAB architecture tpD as fast as 15 ns Counter frequencies up to 83.3 MHz Pipelined data rates up to 100 MHz

L372

Abstract: RCA-CD4085
Contextual Info: G E SOLI» STATE Gl 3875081 G E SOLID STATE D E | 3fl7SDfll DD13BL3 5 01E 13313 D CD4085B Types CMOS Dual 2-Wide 2-lnput AND-OR-INVERT Gate High-Voltage Types 20 -V o lt Rating The RCA-CD4085 contains a pair of ANDOR-INVERT gates, each consisting of two

EA 002-04

Contextual Info: SbE D • 7 ^ 2 3 7 003^330 SCS-THOMSON G s“ s 'ib? - t h o iw o * ¡HilCTIMKSS l ■SGTH TSG8550 T - Í H - O S SWITCHED CAPACITOR MASK PROGRAMMABLE FILTER ■ ■ ■ ■ ■ ■ ■ ■ 6TH ORDER SELECTIVITY FACTOR : Q = 7 GAIN AT CENTER FREQUENCY: OdB typ

cmps a44

Contextual Info: 13 13.1 INSTRUCTION SET OVERVIEW The instruction set used by the Am186EM and Am188EM microcontrollers is identical to the 80C186/188 instruction set. An instruction can reference from zero to several operands. An operand can reside in a register, in the instruction itself, or in memory.

LM015

Abstract: H2535 H2572 LM200 lcd LM038 LM016 H2532A HD61380 H2570 H2525
Contextual Info: HITACHI DOT MATRIX LCD M ODULES H IT A C H I DOT-MATRIX LCD MODULES FROM HITACHI P.O. Box 56310, Pinegowrie 2123 -Tel. 789-1400_ PREFACE H ita c h i D o t M a trix L iq u id C rystal D isplay L C D M od ule was developed to d isp la y num erals, alph abe t, sym bo ls, graphics, etc.

8d02

Contextual Info: SD78K/0 SCREEN DEBUGGER 7. SD78K/0 SCREEN DEBUGGER The SD78K/0 screen debugger is a support software package which connects the ¡E-7800G-RHo* to the host machine PC-9800 Series or IBM PC/AT and its compatible machine and debugs 78K/0 Series programs effectively. The SD78K/

Contextual Info: CY7C1331 CY7C1332 ADVANCED INFORMATION 64K x 18 Synchronous Cache 3.3 V RAM Direct interface with the processor and external cache controller Asynchronous output enable JEDEC-standard pinout 52-pin PLCC and PQFP packaging Features • Supports 66-MHz Pentium proces­

N41 1600

Abstract: n41 ol B65803-J-R67 B65813-J-R47 B65807-C1000-K26 B65803JR67 B65816A1011D1 B65805N125G48 B65613 n30 ol
Contextual Info: RM Cores Example of an assem bly set A d ju s tin g s c re w d riv e r fo r a s s e m b ly o n ly A d ju s tin g s c re w C ore C lam p s In s u la tin g w a s h e r 1 C oil fo rm e r C ore T h re a d e d sle e v e (g lu e d -in ) In su la tin g w a s h e r 2

Contextual Info: CYPRESS ADVANCED INFORMATION 64K x 18 Synchronous Cache 3.3V RAM The CY7C1331 is designed for Intel Pen­ tium and i486 CPU—based systems; its counter follows the burst sequence of the Pentium and the i486 processors. The CY7C1332 is architected for processors

Contextual Info: CY7C1331 CY7C1332 ADVANCED INFORMATION CYPRESS SEMICONDUCTOR Features • Direct interface with the processor and external cache controller • Supports 50-M Hz Pentium processor cache systems with zero wait states • Asynchronous output enable T h e CY7C1331 is designed fo r Intel Pen­

Contextual Info: 5 / CYPRESS CY7C1331 CY7C1332 ADVANCED INFORMATION 64K x 18 Synchronous Cache 3.3V RAM F e a tu re s • D irect interface with th e processor and external cache controller S upports 66-M H z P en tiu m proces­ sor cache system s w ith zero w ait states

71V67603

Abstract: 71V67803
Contextual Info: 256K X 36, 512K X 18 3.3V Synchronous SRAMs 3.3V I/O, Burst Counter Pipelined Outputs, Single Cycle Deselect Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ IDT71V67603 IDT71V67803 256K x 36/512K x 18. The IDT71V67603/7803 SRAMs contain write, data, address and control registers. Internal logic allows the SRAM to

5310

Abstract: gw 340 input id IDT71V67603 IDT71V67802 IDT71V67803 71V67603 71V67803
Contextual Info: 256K X 36, 512K X 18 3.3V Synchronous SRAMs 3.3V I/O, Burst Counter Pipelined Outputs, Single Cycle Deselect Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ IDT71V67603 IDT71V67803 256K x 36/512K x 18. The IDT71V67603/7803 SRAMs contain write, data, address and control registers. Internal logic allows the SRAM to

IDT71V67603

Abstract: IDT71V67802 it 7803 71V67603 71V67803
Contextual Info: 256K X 36, 512K X 18 IDT71V67603/Z 3.3V Synchronous SRAMs IDT71V67803/Z 3.3V I/O, Burst Counter Pipelined Outputs, Single Cycle Deselect Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ 256K x 36/512K x 18. The IDT71V67603/7803 SRAMs contain write, data, address and control registers. Internal logic allows the SRAM to

5310

Abstract: IDT71V67603 IDT71V67802 71V67603 71V67803
Contextual Info: 256K X 36, 512K X 18 IDT71V67603/Z 3.3V Synchronous SRAMs IDT71V67803/Z 3.3V I/O, Burst Counter Pipelined Outputs, Single Cycle Deselect Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ 256K x 36/512K x 18. The IDT71V67603/7803 SRAMs contain write, data, address and control registers. Internal logic allows the SRAM to

71V67603

Abstract: 71V67803
Contextual Info: 256K X 36, 512K X 18 3.3V Synchronous SRAMs 3.3V I/O, Burst Counter Pipelined Outputs, Single Cycle Deselect Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ IDT71V67603 IDT71V67803 256K x 36/512K x 18. The IDT71V67603/7803 SRAMs contain write, data, address and control registers. Internal logic allows the SRAM to

IDT71V67603

Abstract: IDT71V67802 IDT71V67803 133-166MHz 71V67603 71V67803
Contextual Info: 256K X 36, 512K X 18 3.3V Synchronous SRAMs 3.3V I/O, Burst Counter Pipelined Outputs, Single Cycle Deselect Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ IDT71V67603 IDT71V67803 256K x 36/512K x 18. The IDT71V67603/7803 SRAMs contain write, data, address and control registers. Internal logic allows the SRAM to

71V67803

Contextual Info: 256K X 36, 512K X 18 3.3V Synchronous SRAMs 3.3V I/O, Burst Counter Pipelined Outputs, Single Cycle Deselect Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ Advance Information IDT71V67603 IDT71V67803 256K x 36/512K x 18. The IDT71V67603/7803 SRAMs contain write,

71V67603

Abstract: 71V67803
Contextual Info: 256K X 36, 512K X 18 3.3V Synchronous SRAMs 3.3V I/O, Burst Counter Pipelined Outputs, Single Cycle Deselect Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ Advance Information IDT71V67603 IDT71V67803 data, address and control registers. Internal logic allows the SRAM to

71V67603

Abstract: 71V67803
Contextual Info: 256K X 36, 512K X 18 IDT71V67603/Z 3.3V Synchronous SRAMs IDT71V67803/Z 3.3V I/O, Burst Counter Pipelined Outputs, Single Cycle Deselect Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ 256K x 36/512K x 18. The IDT71V67603/7803 SRAMs contain write, data, address and control registers. Internal logic allows the SRAM to

Contextual Info: N EC ELECTRONICS INC b?E D • L427SES DD3^31S 321 HINECE JJPD78356 Family ftiPD78355/356/P356 NEC Electronics Inc. 16-/8-Bit, K-Series Microcontrollers W ith A/D Converter and Convolution Capability September 1993

Contextual Info: LI C Q /I '7 D rl" ü 0 4 / 30 -1000 MHz Standard Hybrid Amplifier Parameters 3 0 -1 0 0 0 M H z bandwidth Specification limit +25 Temperature dB M ax 0.9 1.4 dB M ax p-p Reverse isolation 22 22 dB Min Input 1.7:1 1.8:1 M ax Output 1.8:1 1.9:1 M ax + 10 +9

kx-5t

Abstract: ZTE0
Contextual Info: bSE D • SSÖ'ibbS QGlüllH Features • Supports 50-MHz Pentium proces­ sor cache systems with zero wait states • 64K by 18 common I/O • Fast clock-to-output times — 12.5 ns with 0-pF load —■ 14 ns with 85-pF load • Two-bit w raparound counter support­