F100102 Search Results

F100102DC

Contextual Info: F100102 Quint 2-Input OR/NOR Gate F100K ECL Product Connection Diagrams Description The F100102 is a monolithic quint 2-input OR/NOR gate with common enable. Ail inputs have 50 kO pull-down resistors and all outputs are buffered. Pin Names Dna- Dne E O a-O e

Contextual Info: Section 3 Contents F100101 Triple 5-Input OR/NOR G a te . F100102 Quint 2-Input OR/NOR Gate .

F100102

Abstract: F100302 9836-1
Contextual Info: a National Semiconductor F100102 Quint 2-Input OR/NOR Gate General Description The F100102 is a monolithic quint 2-input OR/NOR gate with common enable. All inputs have 50 k fl pull-down resis­ tors and all outputs are buffered. Ordering Code: Refer to the F100302 datasheet for:

100102DC

Contextual Info: 100102 National Semiconductor F100102 Quint 2-Input OR/NOR Gate General Description R efer to th e F100302 datasheet for: PCC packaging Low er pow er M ilitary versions E xtended voltage specs - 4 . 2 V to - 5 .7 V The F100102 is a m onolithic quint 2-input O R /N O R gate

F100102

Contextual Info: F100102 Quint 2-Input OR/NOR Gate K Ï 5S H E S A Schlumberger Company F10K ECL Product Connection Diagrams Description The F100102 is a monolithic quint 2-input OR/NOR gate with common enable. All inputs have 50 k ll pull-down resistors and all outputs are buffered.

100102DC

Contextual Info: 100102 National Semiconductor F100102 Quint 2-Input OR/NOR Gate General Description The F100102 is a monolithic quint 2-input OR/NOR gate with common enable. All inputs have 50 k fl pull-down resis­ tors and all outputs are buffered. Ordering Code: Refer to the F100302 datasheet for:

Contextual Info: F100102 Quint 2-Input OR/NOR Gate FAIRCHILD A Schlumberger Company F10K ECL Product Description The F100102 is a m on olithic q u in t 2-input O R/NO R gate w ith com m on enable. All inputs have 50 k il pull-dow n resistors and all outputs are buffered. Pin Names

Contextual Info: SEfllCOND LOGIC 31E D • bSG1152 0071052 1 National Semiconductor F100102 Quint 2-Input OR/NOR Gate General Description The F100102 is a monolithic quint 2-input OR/NOR gate with common enable. All inputs have 50 k fi pull-down resis­ tors and all outputs are buffered.

KP590KH5

Abstract: KP590KH4 K590KH5 KP590KH2 DM8136 K591KH1 KP590KH8A K555 KP590KH1 KP590KH3
Contextual Info: INTEGRATED MICROCIRCUITS Electron Device Mfg.Corp CONTENTS 1. Analog low-power M O S switches and multiplexers series K, KP190, 590, 591 3 series K100, K500 . 12 3. E C L nanosecond range microcircuits seriesKH1500 .

F100K ECL Users Handbook

Abstract: F100101 3R12E b2teq AN-674 C1995 DP83231 DP83241 DP83251 DP83261
Contextual Info: National Semiconductor Application Note 674 Bruce Wolfson January 1991 This application note covers basic PCB layout recommendations and design techniques for high speed signal distribution in National’s FDDI system Due to the high signal speeds in FDDI proper layout is critical Many digital designers are not aware of problems that can arise in a high speed

transistor cross reference

Abstract: MPT3N40 Westinghouse SCR handbook LT 8224 ZENER DIODE sje389 N9602N npn transistor RCA 467 TFK 7 segment displays PUT 2N6027 delco 466
Contextual Info: C K TBD DOLLY LIST LOGO LIST SAFETY & RELIABLTY TEK PN SYSTEM II DIGITAL IC's MEMORIES. MOS. CM OS.ECL. TTL MICROPROCESSOR SPECIAL FUNCTION IC's DIGITAL / LINEAR ARRAYS LINEAR IC'S (PURCH) TEK-MADE IC’s 3 IC's INDEX (COLORED PGS) INCL PRGMD. SCRND.ETC

F100302

Abstract: 105604 F100102 F100K EL98
Contextual Info: 100302 National Éià Semiconductor F100302 Low Power Quint 2-Input OR/NOR Gate General Description Features The F100302 is a monolithic quint 2-input OR/NOR gate with common enable. All inputs have 50 k ft pull-down resis­ tors and all outputs are buffered.

Contextual Info: F100K INTRODUCTION Competitive pressure in the data processing industry, with ever-increasing data volumes and new architec­ tures, has stimulated the need for faster processing rates, higher machine densities, and greater system reliability. These requirements can only be met by the use of higher speed integrated circuits with more onchip integration and multipurpose logic functions. Advanced packaging techniques and optimum system